公开(公告)号：US07106563B2

公开(公告)日：2006-09-12

申请号：US10826725

申请日：2004-04-15

Applicant: Chun Hsiang Lai ,  Meng Huang Liu ,  Tao Cheng Lu

Inventor： Chun Hsiang Lai ,  Meng Huang Liu ,  Tao Cheng Lu

IPC: H02H9/00 ,  H02H3/22 ,  H02H3/20 ,  H02H9/04

CPC classification number: H01L27/0251 ,  H01L29/87

Abstract: An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage, so as to discharge the electrostatic charges. The anti-latch-up circuit has two terminals, which are respectively coupled to the voltage source and the ground voltage, and another connection terminal, used to send an anti-latch-up signal to the SCR for changing the activating rate. The latch-up phenomenon is avoided.

Abstract translation: I / O焊盘ESD保护电路由SCR电路，第一二极管，第二二极管和防闩锁电路组成。 SCR电路具有分别耦合到I / O焊盘和接地电压的第一连接端子和第二连接端子，以便放电静电电荷。 防闩锁电路具有分别耦合到电压源和接地电压的两个端子，以及用于向SCR发送防闩锁信号以用于改变激活速率的另一个连接端子。 避免了闩锁现象。

公开(公告)号：US07057938B2

公开(公告)日：2006-06-06

申请号：US10756777

申请日：2004-01-14

Applicant: Chih Chieh Yeh ,  Hung Yueh Chen ,  Yi Ying Liao ,  Wen Jer Tsai ,  Tao Cheng Lu

Inventor： Chih Chieh Yeh ,  Hung Yueh Chen ,  Yi Ying Liao ,  Wen Jer Tsai ,  Tao Cheng Lu

IPC: G11C16/00

CPC classification number: G11C16/10 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit. The present invention also provides a method for sensing and reading at least one bit in a nonvolatile memory comprising applying a bias voltage to the memory, detecting a threshold voltage or read current, comparing the threshold voltage with a reference voltage or comparing the read current with a reference current, and identifying the at least one bit as erased or programmed.

Abstract translation: 本发明的一个实施例提供一种具有非易失性存储器的系统，其包括ap型半导体衬底，p型半导体衬底上的氧化物层，氧化物层上方的氮化物层，氮化物层上的附加氧化物层， 分别形成在两个N +结中的源极和漏极，非易失性存储器中的第一位和第二位，以及相应地至少两个操作状态（即擦除）的附加氧化物层，p型半导体层中的两个N +结， 和程序）。 也就是说，非易失性存储器中的一位可以处于擦除状态或程序状态。 为了擦除一点，电子注入非易失性存储器的栅极。 为了编程一点，注入电孔或减少电子的位。 本发明还提供了一种用于感测和读取非易失性存储器中的至少一个位的方法，包括向存储器施加偏置电压，检测阈值电压或读取电流，将阈值电压与参考电压进行比较，或将读取的电流与 参考电流，并将所述至少一个位识别为擦除或编程。

公开(公告)号：US07031196B2

公开(公告)日：2006-04-18

申请号：US10757073

申请日：2004-01-14

Applicant: Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

Inventor： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC: G11C16/00

CPC classification number: G11C16/0475 ,  G11C16/3468 ,  H01L21/28273 ,  H01L29/792 ,  H01L29/7923

Abstract: A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole to migrate towards and be retained in the trapping layer, and evaluating a read current generated in response to the voltage bias to determine whether a second gate threshold voltage is reached, wherein the second gate threshold voltage is lower than the first gate threshold voltage. The processing sequence is repeated a number of times by varying one or more time the voltage bias between the gate and the first junction region until the second gate threshold voltage is reached and the memory cell is in a program state.

Abstract translation: 一种对存储器单元进行编程的方法包括将存储单元设置为第一栅极阈值电压的初始状态，执行处理顺序，包括：在栅极与第一结区域之间施加电压偏置，使电孔朝向 保持在捕获层中，并且评估响应于电压偏置产生的读取电流，以确定是否达到第二栅极阈值电压，其中第二栅极阈值电压低于第一栅极阈值电压。 通过改变栅极和第一结区域之间的电压偏压的一个或多个时间直到达到第二栅极阈值电压并且存储器单元处于编程状态来重复处理顺序多次。

公开(公告)号：US20060067187A1

公开(公告)日：2006-03-30

申请号：US11257349

申请日：2005-10-24

Applicant: Cheng-Lu Yang ,  Kuo-Eng Wu

Inventor： Cheng-Lu Yang ,  Kuo-Eng Wu

IPC: G11B7/00 ,  G11B7/24

CPC classification number: G11B7/26 ,  G11B23/30

Abstract: An optical disc with an identification tag is provided. The identification tag is an Radio Frequency Identification (RFID) tag provided on the outer rim of the optical disc for storing identification information related to the optical disc, thereby when a plurality of optical discs are packed in a stack, identification information stored in the RFID tags at the outer rims of the optical discs can be easily read.

Abstract translation: 提供具有识别标签的光盘。 识别标签是设置在光盘的外缘上的射频识别（RFID）标签，用于存储与光盘有关的识别信息，从而当多个光盘被堆叠时，存储在RFID中的识别信息 可以容易地读取光盘外缘的标签。

公开(公告)号：US07010705B2

公开(公告)日：2006-03-07

申请号：US10426796

申请日：2003-05-01

Applicant: Kuo-Cheng Lu

Inventor： Kuo-Cheng Lu

IPC: G06F1/32

CPC classification number: G06F1/3231 ,  G06F1/1626 ,  G06F1/1656 ,  G06F1/3203 ,  G06F1/3259 ,  G06F3/03543 ,  Y02D10/155 ,  Y02D10/173

Abstract: A method for triggering a power supply module switch of a cordless electric-apparatus which includes a metal inductive area and an electrostatic inductive element comprising the following steps: when a user body approaches the device to a predetermined distance which is less than the electrostatic induction distance, the electrostatic inductive element detects electrostatic charge from the user body so as to turn a switch within the electrostatic inductive element on; a power supply module supplies power for the cordless electric-apparatus when the switch is turned on; when the user body leaving away from the cordless electric-apparatus exceeds the electrostatic induction distance, the switch within the electrostatic inductive element turns off and when the switch turns off the power supply module supplies a part power for the cordless electric-apparatus.

Abstract translation: 一种用于触发包括金属感应区域和静电感应元件的无绳电气设备的电源模块开关的方法，包括以下步骤：当使用者身体接近小于静电感应距离的预定距离时 静电感应元件检测来自用户体的静电电荷，以使静电感应元件中的开关转动; 当开关打开时，电源模块为无绳电气设备供电; 当离开无绳电气设备的使用者身体超过静电感应距离时，静电感应元件内的开关断开，并且当开关断开时，电源模块为无绳电气设备供电。

公开(公告)号：US06969531B2

公开(公告)日：2005-11-29

申请号：US10649082

申请日：2003-08-26

Applicant: Philip Dehazya ,  Cheng Lu

Inventor： Philip Dehazya ,  Cheng Lu

IPC: A61K9/50 ,  A61K9/62 ,  C08B37/00

CPC classification number: A61K9/5036

Abstract: The present invention relates to microspheres comprising hyaluronan derivatized with a bifunctional crosslinker to form microspheres. Methods of making such microspheres, comprising mixing hyaluronic acid and a dihydrazide with a crosslinker in an aqueous solution, adding a solvent and an emulsifying agent to form an emulsion, and lowering the pH of the emulsion to allow intramolecular and intermolecular crosslinking to occur, are also disclosed. The invention also provides for pharmaceutical or cosmetic formulations based on the microspheres described herein, further containing one or more active or cosmetic agents, and methods of using such formulations.

Abstract translation: 本发明涉及包含用双功能交联剂衍生的透明质酸以形成微球体的微球。 制备这种微球的方法包括将透明质酸和二酰肼与水溶液中的交联剂混合，加入溶剂和乳化剂以形成乳液，并降低乳液的pH以允许发生分子内和分子间交联。 也披露。 本发明还提供了基于本文所述的微球的进一步含有一种或多种活性或美容剂的药物或化妆品制剂以及使用这些制剂的方法。

公开(公告)号：US20050260864A1

公开(公告)日：2005-11-24

申请号：US10765361

申请日：2004-01-27

Applicant: Tzu-Fang Huang ,  Yung-Cheng Lu ,  Li-Qun Xia ,  Ellie Yieh ,  Wai-Fan Yau ,  David Cheung ,  Ralf Willecke ,  Kuowei Liu ,  Ju-Hyung Lee ,  Farhad Moghadam ,  Yeming Ma

Inventor： Tzu-Fang Huang ,  Yung-Cheng Lu ,  Li-Qun Xia ,  Ellie Yieh ,  Wai-Fan Yau ,  David Cheung ,  Ralf Willecke ,  Kuowei Liu ,  Ju-Hyung Lee ,  Farhad Moghadam ,  Yeming Ma

IPC: C23C16/04 ,  C23C16/40 ,  H01L21/316 ,  H01L21/469 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/31612 ,  C23C16/045 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76829 ,  H01L21/76835 ,  H01L2221/1031

Abstract: A silicon oxide layer is produced by plasma enhanced decomposition of an organosilicon compound to deposit films having a carbon content of at least 1% by atomic weight. An optional carrier gas may be introduced to facilitate the deposition process at a flow rate less than or equal to the flow rate of the organosilicon compounds. An oxygen rich surface may be formed adjacent the silicon oxide layer by temporarily increasing oxidation of the organosilicon compound.

Abstract translation: 氧化硅层通过有机硅化合物的等离子体增强分解产生，以沉积碳原子量至少为1％的膜。 可以引入任选的载气，以便以小于或等于有机硅化合物的流速的流速促进沉积过程。 可以通过暂时增加有机硅化合物的氧化而在氧化硅层附近形成富氧表面。

公开(公告)号：US20050215052A1

公开(公告)日：2005-09-29

申请号：US10810970

申请日：2004-03-26

Applicant: Mong-Song Liang ,  Yung-Cheng Lu ,  Huilin Chang

Inventor： Mong-Song Liang ,  Yung-Cheng Lu ,  Huilin Chang

IPC: H01L21/3105 ,  H01L21/44 ,  H01L21/76 ,  H01L21/768

CPC classification number: H01L21/76826 ,  H01L21/3105 ,  H01L21/76825 ,  H01L21/76828

Abstract: An integrated method comprises providing a low dielectric material, applying a first treatment altering a first property of the low dielectric material, and applying a second treatment altering a second property of the treated low dielectric material and producing a lower dielectric material with better mechanical stability.

Abstract translation: 集成方法包括提供低电介质材料，施加改变低电介质材料的第一特性的第一处理，以及施加改变所处理的低电介质材料的第二特性并产生具有更好的机械稳定性的较低电介质材料的第二处理。

公开(公告)号：US06917073B2

公开(公告)日：2005-07-12

申请号：US10643877

申请日：2003-08-20

Applicant: Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

Inventor： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC: H01L27/115 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L27/115

Abstract: To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

Abstract translation: 为了减少相邻存储单元之间的干扰，改进的ONO闪速存储器阵列在通道两侧的每个存储单元的通道的一侧或两个不同浓度的凹槽的一侧上注入一个口袋，从而导致不对称的存储单元 口袋 因此，当通过频带技术对ONO闪速存储器阵列进行编程或擦除时，相邻存储单元之间不会发生干扰，并且在读取过程中相邻存储单元之间的干扰也被抑制。

公开(公告)号：US06914819B2

公开(公告)日：2005-07-05

申请号：US10653892

申请日：2003-09-04

Applicant: Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jer Tsai ,  Tao-Cheng Lu

Inventor： Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: G11C16/3418 ,  G11C16/0475 ,  G11C16/26

Abstract: A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.

Abstract translation: 一种操作非易失性存储单元的方法，其中所述非易失性存储单元包括字线，第一位线和第二位线，所述方法包括对所述存储器单元进行编程，所述存储单元包括向所述存储单元施加高正偏压 第一位线，对第二位线施加接地偏置，以及向字线施加高负偏压，其中带正电荷的空穴穿过介电层进入捕获层。