Abstract:
The present invention relates to a photoreceiver and method of manufacturing the same. For the purpose of a selective detection of a specific wavelength, if a waveguide type photodetector using a multiple quantum-well layer having a quantum confined stark effect as an optical absorption layer, the wavelength that is absorbed by the stark effect by which the transition energy edge of the optical absorption band is varied depending on the intensity of an electric field applied to the multiple quantum-well layer is varied. Thus, a wavelength selective detection characteristic can be varied simply implemented. The waveguide type photodetector of this structure is integrated on a semi-insulating InP substrate with a heterogeneous bipolar transistor having an n+InP/p+InGaAs/n−InGaAs/n+InGaAsP high-gain amplification characteristic. Thus, a photoreceiver of a high performance and a high sensitivity having a specific wavelength selective detection function that can be used in an optical communication system of a high-performance wavelength-multiplexing mode can be provided.
Abstract translation:光接收器及其制造方法技术领域本发明涉及光接收器及其制造方法。 为了选择性地检测特定波长,如果使用具有量子局限性效应的多量子阱层作为光吸收层的波导型光电检测器,则通过转移能量的斯塔克效应吸收的波长 光吸收带的边缘根据施加到多量子阱层的电场的强度而变化。 因此,可以简单地实现波长选择性检测特性。 该结构的波导型光检测器集成在具有n + InP / p + InGaAs / n-InGaAs / n + InGaAsP高增益放大特性的异质双极晶体管的半绝缘InP衬底上。 因此,可以提供具有可用于高性能波长多路复用模式的光通信系统中的具有特定波长选择性检测功能的高性能和高灵敏度的光接收器。
Abstract:
A method of fabricating a semiconductor laser comprises the steps of sequentially depositing a lower cladding layer, an active layer, a first upper cladding layer, an etching stop layer, a second upper cladding layer and an ohmic contact layer over a compound semiconductor substrate, forming an etching mask over the ohmic contact layer so as to expose channel regions and to shield the ridge regions between the channel regions, performing wet etching to etch the ohmic contact layer and the second upper cladding layer so as to expose the etching stop layer so as to form the channels and the ridges having narrower widths than the parts of the etching mask shielding the ridge regions, and implanting dopant ions into the parts of the first upper cladding layer and the active layer below the channels to form ion-implanted regions by using the etching mask as the ion implantation mask.
Abstract:
Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.
Abstract:
The inventive concept relates to an optical communication module. The optical communication module may include a metal block: an electrical device formed on the metal block; an optical device adhesive block formed on the metal block; an optical device formed on the optical device adhesive block and connected to the electrical device through a bonding interconnection; and a flat type optical waveguide formed on one side of the optical device adhesive block and optically aligned with the optical device.
Abstract:
Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.
Abstract:
Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode;and a metal configured to connect the field plate and the source electrode.
Abstract:
Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.
Abstract:
The present disclosure relates to a planar optical waveguide element, and more particularly, to an optical waveguide end structure for effective optical signal connection with a light source, a light receiving element, or a different type of optical waveguide element.According to an exemplary embodiment of the present disclosure, there is disclosed an optical waveguide structure, including: a planar optical waveguide including a lower clad, a waveguide core formed on the lower clad, and a clad layer formed on the waveguide core; and an optical lens formed on a surface of the clad layer.One end of the optical waveguide forms an inclined surface having a predetermined inclination angle.
Abstract:
Provided is a feedback amplifier including: an amplification circuit unit to generate an output voltage by amplifying an input voltage inputted through an input terminal; an output circuit unit to output the generated output voltage through an output terminal; a feedback circuit unit to control the gain of the amplification circuit unit by determining a total feedback resistance value using an external control signal and controlling an input current while the total feedback resistance value is determined; and a bias circuit unit to apply a bias voltage to the feedback circuit unit.
Abstract:
Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on the capping layer. A dielectric interlayer is formed on the substrate, and resist layers having first and second openings with asymmetrical depths are formed on the dielectric interlayer between the source electrode and the drain electrode. The first opening exposes the dielectric interlayer, and the second opening exposes the lowermost of the resist layers. The dielectric interlayer in the bottom of the first opening and the lowermost resist layer under the second opening are simultaneously removed to expose the capping layer to the first opening and expose the dielectric interlayer to the second opening. The capping layer of the first opening is removed to expose the active layer. A metal layer is deposited on the substrate to simultaneously form a gate electrode and a field plate in the first opening and the second opening. The resist layers are removed to lift off the metal layer on the resist layers.