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    High current lateral GaN transistors with scalable topology and gate drive phase equalization
    61.
    发明授权
    High current lateral GaN transistors with scalable topology and gate drive phase equalization 有权

    公开(公告)号：US10218346B1

    公开(公告)日：2019-02-26

    申请号：US15704458

    申请日：2017-09-14

    Applicant: GaN Systems Inc.

    Inventor： Ahmad Mizan ,  Greg P. Klowak ,  Xiaodong Cui

    IPC: H01L29/20 ,  H01L23/522 ,  H01L29/778 ,  H03K17/081 ,  H01L29/205 ,  H01L23/528 ,  H01L29/06 ,  H01L23/532 ,  H01L23/31

    Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.

    Distributed driver circuitry integrated with GaN power transistors
    63.
    发明授权
    Distributed driver circuitry integrated with GaN power transistors 有权

    公开(公告)号：US09660639B2

    公开(公告)日：2017-05-23

    申请号：US15091867

    申请日：2016-04-06

    Applicant: GaN Systems Inc.

    Inventor： John Roberts ,  Ahmad Mizan

    IPC: H03K3/00 ,  H03K17/16 ,  H03K17/687 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417

    CPC classification number: H03K17/162 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H03K17/168 ,  H03K17/6877

    Abstract: Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

    GATE INPUT PROTECTON FOR DEVICES AND SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS
    64.
    发明申请
    GATE INPUT PROTECTON FOR DEVICES AND SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS 审中-公开
    用于包含高功率E型GaN晶体管的器件和系统的栅极输入保护

    公开(公告)号：US20160307886A1

    公开(公告)日：2016-10-20

    申请号：US15131309

    申请日：2016-04-18

    Applicant: GaN Systems Inc.

    Inventor： John ROBERTS ,  Hugues LAFONTAINE

    IPC: H01L27/02 ,  H01L29/778 ,  H01L29/20

    CPC classification number: H01L27/0248

    Abstract: An integrated gate protection device P for a GaN power transistor D1 provides negative ESD spike protection. Protection device P comprises a smaller gate width wg enhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D1, and the source of Pm is connected to the intrinsic source of D1. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors P1 to Pn, connected in series, it turns on when the gate input voltage applied to the drain of P1 goes negative by more than the sum of the threshold voltages of P1 to Pn. The combined gate width of P1 to Pn is selected to limit the gate voltage excursion of D1.

    Abstract translation: 用于GaN功率晶体管D1的集成栅极保护器件P提供负的ESD尖峰保护。 保护器件P包括较小的栅极宽度wg增强型GaN晶体管Pm。 Pm的源极连接到其栅极，Pm的漏极连接到D1的栅极输入，Pm的源极连接到D1的本源。 当门极输入电压为负极低于阈值电压进行反向导通时，Pm导通并熄灭负电压尖峰。 当器件P包括串联连接的多个GaN保护晶体管P1至Pn时，当施加到P1的漏极的栅极输入电压变为负大于P1至Pn的阈值电压之和时，其导通。 选择P1到Pn的组合栅极宽度来限制D1的栅极电压偏移。

    POWER SWITCHING SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS AND DRIVER CIRCUITRY
    65.
    发明申请
    POWER SWITCHING SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS AND DRIVER CIRCUITRY 有权
    包含高功率E型GaN晶体管和驱动电路的电源开关系统

    公开(公告)号：US20160233859A1

    公开(公告)日：2016-08-11

    申请号：US15099459

    申请日：2016-04-14

    Applicant: GaN Systems Inc.

    Inventor： John ROBERTS ,  Iian H. SCOTT

    IPC: H03K17/687 ,  H01L29/20 ,  H03K5/08 ,  H01L29/778

    CPC classification number: H03K17/687 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/7787 ,  H03K5/08 ,  H03K17/04123 ,  H03K2217/0036

    Abstract: Driver circuitry for switching systems comprising enhancement mode (E-Mode) GaN power transistors with low threshold voltage is disclosed. An E-Mode high electron mobility transistor (HEMT) D3 has a monolithically integrated GaN driver, comprising smaller E-Mode GaN HEMTs D1 and D2, and a discrete dual-voltage pre-driver. In operation, D1 provides the gate drive voltage to the gate of the GaN switch D3, and D2 clamps the gate of the GaN switch D3 to the source, via an internal source-sense connection closely coupling the source of D3 and the source of D2. An additional source-sense connection is provided for the pre-driver. Boosting the drive voltage to the gate of D1 produces firm and rapid pull-up of D1 and D3 for improved switching performance at higher switching speeds. High current handling components of the driver circuitry are integrated with the GaN switch and closely coupled to reduce inductance, while the discrete pre-driver can be thermally separated from the GaN chip.

    Abstract translation: 公开了包括具有低阈值电压的增强模式（E模式）GaN功率晶体管的开关系统的驱动电路。 E模式高电子迁移率晶体管（HEMT）D3具有单片集成的GaN驱动器，其包括更小的E型GaN HEMT D1和D2以及分立的双电压预驱动器。 在操作中，D1将栅极驱动电压提供给GaN开关D3的栅极，并且D2通过紧密耦合D3源和D2源的内部源极检测连接将GaN开关D3的栅极钳位到源极 。 为前置驱动程序提供了额外的源感测连接。 将D1和D3的驱动电压提升到D1的栅极，可以实现更快速的D1和D3上拉，从而提高开关速度下的开关性能。 驱动器电路的大电流处理部件与GaN开关集成，并且紧密耦合以减小电感，而离散预驱动器可以与GaN芯片热分离。

    POWER TRANSISTOR CIRCUIT THAT GENERATES INTERNAL VOLTAGE SUPPLY
    67.
    发明申请
    POWER TRANSISTOR CIRCUIT THAT GENERATES INTERNAL VOLTAGE SUPPLY 有权

    公开(公告)号：US20240405768A1

    公开(公告)日：2024-12-05

    申请号：US18327620

    申请日：2023-06-01

    Applicant: GAN SYSTEMS INC.

    Inventor： Nan XING ,  Robert Wayne MOUNGER ,  Lucas Andrew MILNER ,  Krishnaswamy NAGARAJ ,  Sridhar RAMASWAMY ,  Yinglai XIA ,  Edward MACROBBIE

    IPC: H03K17/687

    Abstract: A power transistor circuit suppling an internal voltage to an internal voltage supply node. The power transistor circuit includes external terminals, to each of which signals and/or voltages are applied, for each of the input node, output node and control node of the power transistor. The power transistor circuit includes the power transistor, a current draw transistor, a first diode connected between an external control terminal and the internal voltage supply node, and a second diode connected between the current draw transistor output node and the internal voltage supply node. The power transistor circuit includes a charge pump that receives power from the internal voltage supply node and outputs a voltage to the control node of the current draw transistor. In operation, the internal voltage supply node receives power from the external control terminal via the first diode, or an external input terminal via the current draw transistor and the second diode.

    PACKAGE AND INTEGRATED CIRCUIT WITH INTERFACE DETECTION
    68.
    发明申请
    PACKAGE AND INTEGRATED CIRCUIT WITH INTERFACE DETECTION 有权

    公开(公告)号：US20240403256A1

    公开(公告)日：2024-12-05

    申请号：US18326938

    申请日：2023-05-31

    Applicant: GAN SYSTEMS INC.

    Inventor： Thomas Vermeer

    IPC: G06F13/42

    Abstract: An integrated circuit that is capable of bidirectional communication with an external host device via various communication protocols. In order to determine which communication protocols the incoming signal is using, the integrated circuit further includes an interface detector. When the interface detector determines that the incoming signal represents a portion of a transaction that uses a first communication protocol, the integrated circuit permits the first communication protocol engine to communicate in the transaction. Likewise, when the interface detector determines that the incoming signal represents a portion of a transaction that uses the second communication protocol, the integrated circuit permits the second communication protocol engine to communicate in the transaction. This allows the integrated circuit to detect the protocol regardless of whether one or two package terminals are used in the protocol.

    THERMAL MANAGEMENT SOLUTION FOR POWER STAGE COMPRISING TOP-COOLED POWER SEMICONDUCTOR SWITCHING DEVICES
    69.
    发明公开
    THERMAL MANAGEMENT SOLUTION FOR POWER STAGE COMPRISING TOP-COOLED POWER SEMICONDUCTOR SWITCHING DEVICES 审中-公开

    公开(公告)号：US20240306348A1

    公开(公告)日：2024-09-12

    申请号：US18120046

    申请日：2023-03-10

    Applicant: GaN Systems Inc.

    Inventor： Ruoyu HOU ,  Juncheng LU

    IPC: H05K7/20 ,  H01L23/367 ,  H05K1/02 ,  H05K1/18

    CPC classification number: H05K7/20409 ,  H01L23/3672 ,  H05K1/0216 ,  H05K1/185 ,  H05K2201/066 ,  H05K2201/10166

    Abstract: A power stage assembly for improved thermal dissipation and EMC for top-cooled semiconductor power switching devices, e.g. high voltage, high current lateral GaN power transistors in embedded die packages. The power switching devices are mounted on a PCB substrate, with electrical connections between a bottom side of each device package and the PCB. Each device package has a thermal pad on the top-side. A heat-spreader is secured in thermal contact with the thermal pads of each device, and a heatsink is in thermal contact with the heat-spreader. The heat-spreader is a multilayer structure comprising: a thermally conductive metal substrate layer in contact with the heatsink; a conductive layer providing an EMC layer which is connected to power ground; a conductive layer defining large area thermal pads in thermal contact with thermal pads of each die; and dielectric material electrically isolating conductive layers of the heat-spreader.

    High efficiency resonator coils for large gap wireless power transfer systems
    70.
    发明授权
    High efficiency resonator coils for large gap wireless power transfer systems 有权

    公开(公告)号：US12088115B2

    公开(公告)日：2024-09-10

    申请号：US18494505

    申请日：2023-10-25

    Applicant: GAN SYSTEMS INC.

    Inventor： Tiefeng Shi ,  Paul Wiener

    IPC: H02J50/12 ,  H01F38/14

    CPC classification number: H02J50/12 ,  H01F38/14

    Abstract: High efficiency resonator coils for large gap resonant wireless power transfer (WPT), and a coil design methodology are disclosed. Resonator coils comprise a coil topology defined by coil parameters in which turn dimensions, such as trace widths and spacings of each turn, are configured to reduce or minimize a variance of the z component of magnetic field, over an area of a charging plane at a specified distance, or distance range, from the coil. A Tx resonator coil comprises a capacitor arrangement of tuning and network-matching capacitors for improved coil-to-coil efficiency and end-to-end WPT system performance, e.g. for applications such as through-wall WPT, in the range of tens of watts to at least hundreds of watts. Planar resonator coil topologies are compatible with fabrication using low cost PCB technology, e.g. with multi-layer metal, to reduce losses and improve thermal performance.

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