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    NONVOLATILE SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND ASSOCIATED SYSTEMS
    61.
    发明申请
    NONVOLATILE SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND ASSOCIATED SYSTEMS 有权
    非挥发性半导体器件，包括浮动门和相关系统

    公开(公告)号：US20110156125A1

    公开(公告)日：2011-06-30

    申请号：US13040380

    申请日：2011-03-04

    Applicant: Se-Hoon LEE ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

    Inventor： Se-Hoon LEE ,  Donghoon Jang ,  Jong Jin Lee ,  Jeong-Dong Choe

    IPC: H01L29/788

    CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

    Abstract translation: 存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅 浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

    Motor including stator with metal connection parts and washing machine having the same
    62.
    发明申请
    Motor including stator with metal connection parts and washing machine having the same 有权
    电机包括具有金属连接部件的定子和具有相同的洗衣机

    公开(公告)号：US20100199725A1

    公开(公告)日：2010-08-12

    申请号：US12656191

    申请日：2010-01-20

    Applicant: Woon Yong Lee ,  Jong Jin Lee ,  Myong Gul Choi

    Inventor： Woon Yong Lee ,  Jong Jin Lee ,  Myong Gul Choi

    IPC: D06F25/00 ,  H02K11/00 ,  H02K5/10

    CPC classification number: H02K3/522

    Abstract: Disclosed herein are a motor, which prevents cut-off of magnet wire connection parts due to corrosion caused by a potential difference and damage to a magnet wire film, and a washing machine having the motor. The motor includes a stator, on which a magnet wire is wound, including mag mate terminals connected with the magnet wire, and a rotor rotated by electromagnetic interaction with the stator. Each of the mag mate terminals includes a first metal connection part, to which a metal of a different kind is connected, and a same kind metal connection part, to which a metal of the same kind is connected.

    Abstract translation: 这里公开了一种电动机，其防止由电位差引起的腐蚀和电磁线膜的损坏导致的电磁线连接部的切断，以及具有电动机的洗衣机。 该电动机包括：定子，其上缠绕有电磁线，包括与电磁线连接的磁偶合端子以及通过与定子的电磁相互作用旋转的转子。 每个磁电偶端子包括与其连接的不同种类的金属的第一金属连接部分和相同种类的金属连接的相同种类的金属连接部分。

    SMALL-SIZED FUSE BOX AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME
    63.
    发明申请
    SMALL-SIZED FUSE BOX AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME 有权
    小尺寸保险丝盒和半导体集成电路

    公开(公告)号：US20100165774A1

    公开(公告)日：2010-07-01

    申请号：US12483440

    申请日：2009-06-12

    Applicant: Jong Jin LEE

    Inventor： Jong Jin LEE

    IPC: G11C17/16 ,  H01H85/00 ,  G11C8/00

    CPC classification number: H01H85/0241 ,  G11C17/16 ,  G11C29/787 ,  H01H2085/0275 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed are a fuse box and a semiconductor integrated circuit having the same. The semiconductor integrated circuit includes a plurality of banks, column control blocks, and column fuse blocks. The plurality of banks including a plurality of mat rows and mat columns. The banks are arranged in row and column directions and disposed away from each other. The column control blocks are disposed in a space between the banks which are extended to the column direction. The column fuse blocks are disposed adjacent to the column control blocks and have a plurality of fuse boxes. The fuse boxes include fuse sets arranged in two rows. The fuse boxes are disposed to correspond to the one mat column. Each fuse box has an interconnection fuse and address fuses which are arranged with a constant interval and are the same type.

    Abstract translation: 公开了一种保险丝盒和具有该保险丝盒的半导体集成电路。 半导体集成电路包括多个组，列控制块和列熔丝块。 多个存储体包括多个垫子行和垫子列。 银行按行和列方向排列，彼此远离。 列控制块设置在延伸到列方向的堤之间的空间中。 列保险丝块被布置成与列控制块相邻并且具有多个保险丝盒。 保险丝盒包括两列排列的保险丝套件。 保险丝盒被设置成对应于一个垫柱。 每个保险丝盒具有互连熔断器和地址保险丝，它们以恒定间隔布置并且是相同类型的。

    METHOD OF MANUFACTURING THROUGH-VIA
    64.
    发明申请
    METHOD OF MANUFACTURING THROUGH-VIA 失效
    通过威胁制造的方法

    公开(公告)号：US20100136783A1

    公开(公告)日：2010-06-03

    申请号：US12604355

    申请日：2009-10-22

    Applicant: Jong-jin Lee ,  Hyun-seo Kang ,  Jai-sang Koh

    Inventor： Jong-jin Lee ,  Hyun-seo Kang ,  Jai-sang Koh

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed is a method of manufacturing a through-via. The through-via manufacturing method includes forming a core-via hole in a wafer, forming a suction-via hole adjacent to the core-via hole in the wafer, forming a via core in the core-via hole, forming a polymer-via hole connected to the suction-via hole in the wafer, filling the polymer-via hole with polymer solution by creating a vacuum inside the polymer-via hole by drawing air out of the suction-via hole, and polishing the wafer such that the via core formed in the core-via hole is exposed.

    Abstract translation: 公开了一种制造通孔的方法。 通孔制造方法包括在晶片中形成芯通孔，在晶片中形成与芯通孔相邻的吸通孔，在芯通孔中形成通孔，形成聚合物通孔 孔连接到晶片中的吸孔通孔，通过将聚合物通孔中的空气抽出吸出通孔，通过在聚合物通孔内产生真空来填充聚合物通孔，并抛光晶片，使得通孔 在芯通孔中形成的芯露出。

    CMOS IMAGE SENSOR CONFIGURED TO PROVIDE REDUCED LEAKAGE CURRENT
    66.
    发明申请
    CMOS IMAGE SENSOR CONFIGURED TO PROVIDE REDUCED LEAKAGE CURRENT 有权
    CMOS图像传感器被配置为提供减少的漏电流

    公开(公告)号：US20090230444A1

    公开(公告)日：2009-09-17

    申请号：US12403794

    申请日：2009-03-13

    Applicant: Ju-hyun Ko ,  Jong-jin Lee ,  Jung-chak Ahn

    Inventor： Ju-hyun Ko ,  Jong-jin Lee ,  Jung-chak Ahn

    IPC: H01L31/112

    CPC classification number: H01L27/14603

    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) includes a semiconductor substrate including a photodiode therein as a light sensing unit. A floating diffusion region of a first conductivity type is provided in the semiconductor substrate, and is configured to receive charges generated in the photodiode. A power supply voltage region of the first conductivity type is also provided in the semiconductor substrate. A reset transistor including a reset gate electrode on a surface of the substrate between the floating diffusion region and a power supply voltage region is configured to discharge charges stored in the floating diffusion region in response to a reset control signal. The reset transistor includes a channel region in the substrate extending between the floating diffusion region and the power supply voltage region such that the floating diffusion region and the power supply voltage regions define source/drain regions for the reset transistor. An impurity region is provided in a first portion of the channel region adjacent to the floating diffusion region. The impurity region has a doping such that the first portion of the channel region adjacent to the floating diffusion region has a different built-in potential than a second portion of the channel region adjacent to the power supply voltage region.

    Abstract translation: 互补金属氧化物半导体（CMOS）图像传感器（CIS）包括其中包括其中的光电二极管作为光感测单元的半导体衬底。 第一导电类型的浮动扩散区域设置在半导体衬底中，并且被配置为接收在光电二极管中产生的电荷。 第一导电类型的电源电压区域也设置在半导体衬底中。 包括在浮置扩散区域和电源电压区域之间的衬底表面上的复位栅电极的复位晶体管被配置为响应于复位控制信号而放电存储在浮动扩散区域中的电荷。 所述复位晶体管包括在所述衬底中的在所述浮动扩散区域和所述电源电压区域之间延伸的沟道区域，使得所述浮动扩散区域和所述电源电压区域限定所述复位晶体管的源极/漏极区域。 杂质区设置在与浮动扩散区相邻的沟道区的第一部分中。 杂质区域具有使得与浮动扩散区域相邻的沟道区域的第一部分具有与与电源电压区域相邻的沟道区域的第二部分不同的内置电位的掺杂。

    Memory devices and methods of manufacturing the same
    69.
    发明申请
    Memory devices and methods of manufacturing the same 审中-公开
    存储器件及其制造方法

    公开(公告)号：US20080105927A1

    公开(公告)日：2008-05-08

    申请号：US11711117

    申请日：2007-02-27

    Applicant: Young-Joon Ahn ,  Jong-Jin Lee

    Inventor： Young-Joon Ahn ,  Jong-Jin Lee

    IPC: H01L29/94 ,  H01L21/336

    CPC classification number: H01L27/11521 ,  H01L21/764 ,  H01L27/115 ,  H01L29/40114

    Abstract: The memory device includes upper gate structures and lower gate structures formed on an active region of a substrate, and an insulation layer. Each of the upper gate structures may have a blocking layer pattern and a control gate electrode. Each of the lower gate structures may have a tunnel insulation layer pattern and a floating gate electrode. The floating gate electrode may include a lower portion that is narrower than an upper portion contacting with the upper gate structure. The insulation layer may cover gate structures formed of the lower and upper gate structures, and may include air gaps between adjacent gate structures.

    Abstract translation: 存储器件包括形成在衬底的有源区上的上栅极结构和下栅极结构以及绝缘层。 每个上部栅极结构可以具有阻挡层图案和控制栅电极。 每个下栅极结构可以具有隧道绝缘层图案和浮栅电极。 浮栅电极可以包括比与上栅极结构接触的上部更窄的下部。 绝缘层可以覆盖由下部和上部栅极结构形成的栅极结构，并且可以包括相邻栅极结构之间的气隙。

    Memory device and method of manufacturing the same
    70.
    发明申请
    Memory device and method of manufacturing the same 有权
    存储器件及其制造方法

    公开(公告)号：US20080067580A1

    公开(公告)日：2008-03-20

    申请号：US11710488

    申请日：2007-02-26

    Applicant: Young-Joon Ahn ,  Suk-Pil Kim ,  Jong-Jin Lee

    Inventor： Young-Joon Ahn ,  Suk-Pil Kim ,  Jong-Jin Lee

    IPC: H01L29/792 ,  H01L21/336

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/4991 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/792

    Abstract: In a memory device and a method of manufacturing the memory device, a pair of channel layers included in the memory device may be formed on a sidewall of the sacrificial single crystalline layer pattern located on a protrusion of a semiconductor substrate. Accordingly, an etch damage may be reduced at the channel layer. The sacrificial single crystalline layer pattern may be removed to generate a void between the pair of the channel layers. As a result, a generation of a coupling effect may be reduced between the channel layers.

    Abstract translation: 在存储器件和存储器件的制造方法中，包括在存储器件中的一对沟道层可以形成在位于半导体衬底的突起上的牺牲单晶层图案的侧壁上。 因此，在沟道层可能会减少蚀刻损伤。 可以去除牺牲单晶层图案以在一对通道层之间产生空隙。 结果，可以在沟道层之间产生耦合效应。

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