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    POWER AMPLIFIER
    61.
    发明申请
    POWER AMPLIFIER 失效
    功率放大器

    公开(公告)号：US20080061871A1

    公开(公告)日：2008-03-13

    申请号：US11687770

    申请日：2007-03-19

    Applicant: Kazuhide ABE ,  Tadahiro SASAKI ,  Kazuhiko ITAYA ,  Hideyuki FUNAKI

    Inventor： Kazuhide ABE ,  Tadahiro SASAKI ,  Kazuhiko ITAYA ,  Hideyuki FUNAKI

    IPC: H03F1/14

    CPC classification number: H03F3/2176 ,  H03F1/02 ,  H03F3/245 ,  H03F2200/366 ,  H03F2200/391 ,  H03F2203/21178 ,  H03G1/0088

    Abstract: A power amplifier includes: a plurality of field effect transistors connected in parallel and each having a first and second ends, the first end being connected to ground; an amplifying unit which includes at least one of an inductor, a capacitor and a band pass filter and has a third and fourth ends, the third end being connected to the second ends of the field effect transistors, and the fourth end outputting an amplified output signal; and an amplitude controller which sends control signals respectively to gates of the field effect transistors to turn on or off the field effect transistors based on an address signal for performing selection on the field effect transistors and a clock signal. Channel widths of the field effect transistors are different from each other.

    Abstract translation: 功率放大器包括：多个并联连接的场效应晶体管，每个具有第一和第二端，所述第一端连接到地; 放大单元，其包括电感器，电容器和带通滤波器中的至少一个，并具有第三和第四端，第三端连接到场效应晶体管的第二端，第四端输出放大的输出 信号; 以及幅度控制器，其基于用于对场效应晶体管进行选择的地址信号和时钟信号，分别向场效应晶体管的栅极发送控制信号以导通或关闭场效应晶体管。 场效应晶体管的沟道宽度彼此不同。

    Production method for wiring structure of semiconductor device
    62.
    发明授权
    Production method for wiring structure of semiconductor device 有权
    半导体器件布线结构的生产方法

    公开(公告)号：US07211505B2

    公开(公告)日：2007-05-01

    申请号：US11230525

    申请日：2005-09-21

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/4763

    CPC classification number: H01L23/53295 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring films formed protrusively above tops of the first insulating film among the grooves, plural barrier films formed on bottoms of the wiring films and up to a position on sides of the wiring films higher than the tops of the first insulating film; first cap films comprising metal films formed on tops of the wiring films, and a second cap film formed on at least respective sides of the first cap films and the barrier films.

    Abstract translation: 在半导体器件的布线结构中，通过防止布线材料的扩散，提高布线的电介质公差。 半导体器件的布线结构包括具有多个沟槽的第一绝缘膜，多个布线膜，突出地形成在沟槽中的第一绝缘膜的顶部上方，多个阻挡膜形成在布线膜的底部，直到第 所述布线膜高于所述第一绝缘膜的顶部; 第一盖膜包括形成在布线膜的顶部上的金属膜，以及形成在第一盖膜和阻挡膜的至少各个侧面上的第二盖膜。

    Method of forming plug
    63.
    发明授权
    Method of forming plug 有权
    形成插头的方法

    公开(公告)号：US07192858B2

    公开(公告)日：2007-03-20

    申请号：US10352871

    申请日：2003-01-29

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/44

    CPC classification number: H01L21/76831 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76832

    Abstract: A method of producing a semiconductor device includes, in order to electrically connect a lower layer wiring and an upper layer wiring opposite to each other with an interlayer insulation film intervening between them, a step of forming a via-hole, which exposes the lower layer wiring upward from the lower layer wiring through the interlayer insulation film, a step of forming a protective film for preventing erosion, and a step of forming a plug for electrically connecting the lower layer wiring to the upper layer wiring, wherein the protective film is formed by a CVD process in order to cover a residue having stuck to the inner wall of the hole concerned during forming the via-hole.

    Abstract translation: 一种制造半导体器件的方法包括：为了将下层布线和彼此相对的上层布线与介于其间的层间绝缘膜电连接，形成通孔的步骤，其使下层 通过层间绝缘膜从下层布线向上布线，形成用于防止侵蚀的保护膜的步骤以及形成用于将下层布线电连接到上层布线的插塞的步骤，其中形成保护膜 通过CVD工艺以覆盖在形成通孔期间粘附到相关孔的内壁上的残留物。

    Digital signal demodulator and wireless receiver using the same
    64.
    发明申请
    Digital signal demodulator and wireless receiver using the same 失效
    数字信号解调器和无线接收机使用相同

    公开(公告)号：US20060103561A1

    公开(公告)日：2006-05-18

    申请号：US11268615

    申请日：2005-11-08

    Applicant: Kazuhide Abe ,  Michihiko Nishigaki ,  Toshihiko Nagano ,  Takashi Kawakubo

    Inventor： Kazuhide Abe ,  Michihiko Nishigaki ,  Toshihiko Nagano ,  Takashi Kawakubo

    IPC: H03M3/00

    CPC classification number: H04L27/2276

    Abstract: A digital demodulator includes a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a digital signal modulated by phase shift keying, a capacitor to store the charge of the resonator, an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal, and a controller configured to accumulate in the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier.

    Abstract translation: 数字解调器包括具有与载波频率相同的谐振频率的谐振器，以存储与通过相移键控调制的数字信号相对应的电荷，存储谐振器的电荷的电容器，包括输入节点和输出节点的放大器 其间连接有电容器以将存储的电容器的电荷转换成电压信号，以及控制器，被配置为在第一控制模式中在谐振器中累积由相移键控调制的频率信号引起的电荷， 在第二控制模式下将谐振器充电到电容器，以从放大器的输出节点输出与电容器的存储电荷相对应的电压信号。

    Filter control apparatus and filter system
    67.
    发明申请
    Filter control apparatus and filter system 审中-公开
    过滤器控制装置和过滤系统

    公开(公告)号：US20050280476A1

    公开(公告)日：2005-12-22

    申请号：US11151343

    申请日：2005-06-14

    Applicant: Kazuhide Abe ,  Michihiko Nishigaki ,  Toshihiko Nagano ,  Ryoichi Ohara ,  Hiroshi Yoshida ,  Hiroshi Tsurumi ,  Takashi Kawakubo

    Inventor： Kazuhide Abe ,  Michihiko Nishigaki ,  Toshihiko Nagano ,  Ryoichi Ohara ,  Hiroshi Yoshida ,  Hiroshi Tsurumi ,  Takashi Kawakubo

    IPC: H03B21/01 ,  H03H7/01 ,  H03L7/00 ,  H03L7/07 ,  H03L7/081 ,  H03L7/099

    CPC classification number: H03H7/0161 ,  H03B21/01 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/099 ,  H03L7/0995

    Abstract: A filter control apparatus which controls a frequency variable filter capable of changing a transmission band width by controlling a capacitance of at least a portion of a plurality of voltage variable capacitors connected in series and parallel to a resonator has an input unit, and a filter control circuit. The input unit inputs a reference signal with a predetermined reference frequency to the frequency variable filter. The filter control circuit controls a center frequency and the transmission band width of the frequency variable filter by detecting a phase change generated when the reference signal passes through the frequency variable filter and by variably controlling the capacitance of at least a portion of the voltage variable capacitor by using a direct voltage in proportion to the phase change.

    Abstract translation: 控制能够通过控制串联并联到谐振器的多个电压可变电容器的至少一部分的电容来改变传输带宽的滤波器控制装置具有输入单元和滤波器控制 电路。 输入单元将具有预定参考频率的参考信号输入到频率可变滤波器。 滤波器控制电路通过检测当参考信号通过频率可变滤波器时产生的相位变化并且通过可变地控制电压可变电容器的至少一部分的电容来控制频率可变滤波器的中心频率和传输带宽 通过使用与相变成比例的直流电压。

    Method of forming buried wiring in semiconductor device
    68.
    发明申请
    Method of forming buried wiring in semiconductor device 失效

    公开(公告)号：US20050186795A1

    公开(公告)日：2005-08-25

    申请号：US11109634

    申请日：2005-04-20

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

    CPC classification number: H01L21/7685 ,  H01L21/7684 ,  H01L21/76867

    Abstract: A method of forming buried wiring, includes the steps of forming an insulating layer having a trench on a semiconductor substrate; forming a conductive layer mainly composed of copper on the insulating layer in such a manner that the trench is filled with the conductive layer; removing an oxide layer generated in a surface of the conductive layer by oxidation; forming a cap layer made of a material having less mechanical strength than the oxide layer, on the conductive layer; and removing the cap layer and a part of the conductive layer by chemical mechanical polishing in such a manner that the conductive layer is left in the trench.

    Method for forming an interconnection in a semiconductor element
    70.
    发明授权
    Method for forming an interconnection in a semiconductor element 有权
    在半导体元件中形成互连的方法

    公开(公告)号：US06903008B2

    公开(公告)日：2005-06-07

    申请号：US10320582

    申请日：2002-12-17

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/4763

    CPC classification number: H01L21/76831 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76859 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76885

    Abstract: There is disclosed a method for forming an interconnection in the semiconductor element, including a process for forming a groove 117 on an underlying substrate so as to correspond to the designed pattern, a process for forming an underlayer to improve crystalline of an interconnection which will be formed in the succeeding stage on said underlying substrate with said groove, a process for forming a thin film of the interconnection material, a heat-treatment process to fill the said groove with the thin film of the interconnection material formed on the underlying substrate, and a process for forming the interconnection by polishing the surface of the thin film by predetermined quantity.

    Abstract translation: 公开了一种用于在半导体元件中形成互连的方法，包括在下面的基底上形成凹槽117以对应于所设计的图案的工艺，用于形成底层以改善互连结晶的方法 在所述下面的基板上形成在所述凹槽中的后续阶段，用于形成互连材料的薄膜的方法，用形成在下面的基板上的互连材料的薄膜填充所述凹槽的热处理工艺，以及 通过以预定量抛光薄膜的表面来形成互连的工艺。

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