公开(公告)号：US09274577B2

公开(公告)日：2016-03-01

申请号：US14490046

申请日：2014-09-18

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Bo-Ming Huang ,  Kuo-Yu Wu

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/263 ,  G06F1/266 ,  G06F1/3212

Abstract: An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode.

Abstract translation: 公开了一种自适应通用串行总线（USB）充电方法和系统。 在低功耗状态下，USB设备以非USB充电模式进行充电。 当不检测到耦合到USB设备的数据信号的变化时，保持非USB充电模式。 当数据信号具有第一周期的变化时，它被切换到第三专有充电模式。

公开(公告)号：US09256554B2

公开(公告)日：2016-02-09

申请号：US13736092

申请日：2013-01-08

Applicant: VIA Technologies, Inc.

Inventor： Shou-Di Li ,  Guang-Hui Wu ,  Hai-Bin Shen

IPC: G06F12/00 ,  G06F12/16 ,  G06F11/14

CPC classification number: G06F11/1438 ,  G06F11/1402 ,  G06F11/1441 ,  G06F12/16 ,  G06F2201/805 ,  G06F2201/85

Abstract: A progress recording method and a corresponding recovering method adapted to an encoding operation performed on a storage area of a storage device are provided. The progress recording method includes the following steps. A variable set is initialized and stored. The encoding operation includes a plurality of sub-operations, and each of the sub-operations is corresponding to at least one flag variable in the variable set. The flag variables are used for recording execution progresses of the sub-operations. When each of the sub-operations is executed, the corresponding flag variable in the variable set is updated according to the execution progress of the sub-operation.

Abstract translation: 提供了一种适用于对存储装置的存储区域执行的编码操作的进度记录方法和相应的恢复方法。 进度记录方法包括以下步骤。 初始化并存储变量集。 编码操作包括多个子操作，并且每个子操作对应于变量集合中的至少一个标志变量。 标志变量用于记录子操作的执行进度。 当执行每个子操作时，根据子操作的执行进度来更新变量集中的相应标志变量。

公开(公告)号：US09246479B2

公开(公告)日：2016-01-26

申请号：US14159191

申请日：2014-01-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yeong-Sheng Lee

IPC: H03L5/00 ,  H03K5/003 ,  H03F3/45

CPC classification number: H03K5/003 ,  G05F3/30 ,  H03F3/45475 ,  H03F3/45982 ,  H03F2203/45212

Abstract: A low-offset bandgap circuit including a core bandgap circuit and an offset-cancelling circuit is provided. The low-offset bandgap circuit provides a reference voltage at an output node. The core bandgap circuit includes a core operational amplifier to generate a core current. The offset-cancelling circuit is coupled to two input terminals of the core operational amplifier. The offset-cancelling circuit is configured to generate a compensation current according to the voltages at the two input terminals of the core operational amplifier so as to compensate for an offset voltage of the core operational amplifier. The reference voltage is generated according to the core current and the compensation current.

Abstract translation: 提供了一种包括内核带隙电路和偏移消除电路的低偏移带隙电路。 低偏移带隙电路在输出节点处提供参考电压。 核心带隙电路包括用于产生核心电流的核心运算放大器。 偏移消除电路耦合到核心运算放大器的两个输入端。 偏移消除电路被配置为根据核心运算放大器的两个输入端处的电压产生补偿电流，以补偿核心运算放大器的偏移电压。 参考电压根据磁芯电流和补偿电流产生。

公开(公告)号：US20160021735A1

公开(公告)日：2016-01-21

申请号：US14534170

申请日：2014-11-06

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K1/182 ,  H05K2201/042 ,  H05K2201/10189

Abstract: A through-hole layout structure is suitable for a circuit board. The through-hole layout structure includes a pair of first differential through-holes, a pair of second differential through-holes, a first ground through-hole, a second ground through-hole, and a third ground through-hole, which are all arranged on a first line.The first ground through-hole is located between the pair of first differential through-holes and the pair of second differential through-holes. The pair of first differential through-holes is located between the first ground through-hole and the second ground through-hole. The pair of second differential through-holes is located between the first ground through-hole and the third ground through-hole.

Abstract translation: 通孔布局结构适用于电路板。 通孔布局结构包括一对第一差分通孔，一对第二差分通孔，第一接地通孔，第二接地通孔和第三接地通孔，这些都是 安排在第一行。 第一接地通孔位于一对第一差分通孔和一对第二差动通孔之间。 一对第一差分通孔位于第一接地通孔和第二接地通孔之间。 一对第二差分通孔位于第一接地通孔和第三接地通孔之间。

公开(公告)号：US09213673B2

公开(公告)日：2015-12-15

申请号：US13772456

申请日：2013-02-21

Applicant: VIA Technologies, Inc.

Inventor： John K. Lee

IPC: G06F15/16 ,  G06F15/167 ,  H04L29/08 ,  G06F9/48

CPC classification number: G06F15/167 ,  G06F9/4843 ,  H04L67/2842 ,  H04L67/34

Abstract: Disclosed are various embodiments for providing networked applications that are segmented into multiple client-cached executable modules. Multiple networked applications are provided by an application server, and a module cache is maintained in a client. The client obtains a user invocation of a particular functionality associated with a networked application. One of the modules associated with the particular functionality is obtained by the client from the application server over a network in response to determining that the module is not already in the module cache. The module is executed by the client to provide the particular functionality. A data cache may be implemented that includes data blocks that have been used, are being used, or are predicted to be used by the networked application.

Abstract translation: 公开了用于提供被分割成多个客户端缓存的可执行模块的网络应用的各种实施例。 多个网络应用程序由应用程序服务器提供，并且模块缓存在客户端中维护。 客户端获得与联网应用​​相关联的特定功能的用户调用。 响应于确定模块尚未在模块高速缓存中，由客户端通过网络从应用服务器获得与特定功能相关联的模块之一。 该模块由客户端执行以提供特定的功能。 可以实现数据高速缓存，其包括已被使用，正被使用或被预测为联网应用使用的数据块。

公开(公告)号：US20150349766A1

公开(公告)日：2015-12-03

申请号：US14607230

申请日：2015-01-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Quanfeng LIU ,  Huijie DUAN

IPC: H03K5/14 ,  H01L23/528 ,  H01L27/092

CPC classification number: H03K5/14 ,  H01L23/528 ,  H01L27/092

Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.

Abstract translation: 提供延迟线路电路，并且包括精细延迟单元和粗略延迟单元。 每个精细延迟电路包括第一PMOS晶体管; 第一NMOS晶体管; 第二PMOS晶体管，其第二PMOS晶体管的栅极特征的宽度相等; 耦合在第一PMOS晶体管的电源电压和源极之间的至少一个第三PMOS晶体管，其栅极特征的宽度小于第二PMOS晶体管的栅极特征的宽度，第二NMOS晶体管的栅极特征的宽度 第二NMOS晶体管相等; 以及耦合在第一NMOS晶体管的接地电压和源极之间的至少一个第三NMOS晶体管，栅极特征的宽度小于第二NMOS晶体管的栅极特征的宽度。

公开(公告)号：US20150347140A1

公开(公告)日：2015-12-03

申请号：US14315122

申请日：2014-06-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Gerard M. Col ,  Matthew Daniel Day

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30069 ,  G06F9/30032 ,  G06F9/384 ,  G06F9/3855

Abstract: A processor performs out-of-order execution of a first instruction and a second instruction after the first instruction in program order, the first instruction includes source and destination indicators, the source indicator specifies a source of data, the destination indicator specifies a destination of the data, the first instruction instructs the processor to move the data from the source to the destination, the second instruction specifies a source indicator that specifies a source of data. A rename unit updates the second instruction source indicator with the first instruction source indicator if there are no intervening instructions that write to the source or to the destination of the first instruction and the second instruction source indicator matches the first instruction destination indicator.

Abstract translation: 处理器以程序顺序执行在第一指令之后的第一指令和第二指令的无序执行，第一指令包括源和目标指示符，源指示符指定数据源，目的地指示符指定 数据，第一指令指示处理器将数据从源移动到目的地，第二指令指定指定数据源的源指示符。 如果没有写入到第一指令的源或目的地的第二指令源指示符，并且第二指令源指示符与第一指令目标指示符匹配，则重命名单元用第一指令源指示符更新第二指令源指示符。

公开(公告)号：US09197454B2

公开(公告)日：2015-11-24

申请号：US14156700

申请日：2014-01-16

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Chun-Che Huang

IPC: H04L27/00 ,  H04L25/02

CPC classification number: H04L25/0272 ,  H04L25/029

Abstract: A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.

Abstract translation: 差分信号发送器电路包括输出驱动电路和漏电流防止电路。 输出驱动器电路被配置为根据电源发送一对差分信号。 泄漏电流防止电路耦合到电源并且被配置为将电源电力耦合到处于通电状态的输出驱动器电路，并且在断电状态下将输出驱动器电路的电源解耦。

公开(公告)号：US20150324283A1

公开(公告)日：2015-11-12

申请号：US14469703

申请日：2014-08-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yi-Lin LAI

IPC: G06F12/02 ,  G11C29/42 ,  G11C29/52 ,  G06F11/10

CPC classification number: G06F3/06 ,  G06F11/1072 ,  G06F12/0246 ,  G06F12/06 ,  G06F2212/7201 ,  G11C29/42 ,  G11C29/52

Abstract: A flash memory control method, storing a logical-to-physical address mapping relationship between a host and a flash memory and a root table in the flash memory and providing a non-volatile storage area storing a root table pointer. A mapping relationship pointer is set forth in the root table to show where the logical-to-physical address mapping relationship is stored in the flash memory. The root table pointer points to the root table stored in the flash memory. In response to a power restoration request issued from the host, the flash memory is accessed based on the root table pointer and thereby the root table is read and the logical-to-physical address mapping relationship is retrieved from the flash memory based on the mapping relationship pointer set forth in the root table.

Abstract translation: 一种闪速存储器控制方法，存储主机与闪速存储器之间的逻辑到物理地址映射关系以及闪速存储器中的根表，并提供存储根表指针的非易失性存储区域。 映射关系指针在根表中列出，以显示逻辑到物理地址映射关系存储在闪存中的位置。 根表指针指向存储在闪存中的根表。 响应从主机发出的电源恢复请求，基于根表指针访问闪存，从而读取根表，并且基于映射从闪存中检索逻辑到物理地址映射关系 关系指针在根表中列出。

公开(公告)号：US09142541B2

公开(公告)日：2015-09-22

申请号：US14076419

申请日：2013-11-11

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L27/02 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines.

Abstract translation: 公开了一种包括顺序地设置在基板上的第一绝缘层和第二绝缘层的半导体器件。 第一导电线和第二导线设置在第一绝缘层中，并且第一和第二导线中的每一个具有第一端和第二端，其中第一和第二导线的第二端耦合到每个 其他。 第一绕组部分和第二绕组部分设置在第二绝缘层中，并且第一和第二绕组部分中的每一个包括从内向外布置的第三导线和第四导线。 第三和第四导线中的每一个具有第一端和第二端，其中第一和第二导线与第三导线的至少一部分重叠。