公开(公告)号：US11892966B2

公开(公告)日：2024-02-06

申请号：US17551132

申请日：2021-12-14

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Ygal Arbel ,  Sagheer Ahmad

IPC: G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0016

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

公开(公告)号：US11876523B1

公开(公告)日：2024-01-16

申请号：US18079649

申请日：2022-12-12

Applicant: XILINX, INC.

Inventor： Hongtao Zhang ,  Ankur Jain ,  Hsung Jai Im

IPC: H03L7/093 ,  H03L7/081 ,  G04F10/00 ,  H03M1/08 ,  H03L7/099

CPC classification number: H03L7/093 ,  G04F10/005 ,  H03L7/081 ,  H03L7/099 ,  H03M1/0854

Abstract: Embodiments herein describe normalizing an output of a TDC in a DPLL to a resolution of the TDC. A DTC can delay a reference clock which is then input into the TDC. The TDC outputs a digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a DCO in the DPLL. This digital code is normalized to a resolution of the TDC and the result is filtered by a DLF.

公开(公告)号：US20240012655A1

公开(公告)日：2024-01-11

申请号：US17862257

申请日：2022-07-11

Applicant: XILINX, INC.

Inventor： Ahmad R. ANSARI ,  David P. SCHULTZ

IPC: G06F9/445

CPC classification number: G06F9/44505

Abstract: Embodiments herein describe a distributed configuration system for a configurable device. Instead of relying solely on a central configuration manager to distribute configuration information to various subsystems in the device, the embodiments herein include configuration interface managers (CIM) that are distributed in different regions of the device, whether those regions are in one integrated circuit or include multiple integrated circuits. The embodiments can still use a central configuration manager to distribute configuration information in a device image to the plurality of CIMs, which can then forward the configuration information to their assigned regions.

公开(公告)号：US20240005074A1

公开(公告)日：2024-01-04

申请号：US17810547

申请日：2022-07-01

Applicant: Xilinx, Inc.

Inventor： Pongstorn Maidee

IPC: G06F30/333 ,  G06F30/343 ,  G01R31/28

CPC classification number: G06F30/333 ,  G06F30/343 ,  G01R31/2889

Abstract: An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.

公开(公告)号：US11847108B2

公开(公告)日：2023-12-19

申请号：US16596581

申请日：2019-10-08

Applicant: XILINX, INC.

Inventor： Steven L. Pope ,  David J. Riddoch ,  Matthew Knight

IPC: G06F16/22 ,  G06F16/23 ,  H04L43/04 ,  H04L43/12 ,  H04L43/028

CPC classification number: G06F16/2272 ,  G06F16/2322 ,  H04L43/028 ,  H04L43/04 ,  H04L43/12

Abstract: A system has data capture devices collecting data from different points in a network. The captured data is written to a data store and is directed to an output. The data from the different data capture devices can be delivered to a data analytics device. As long as the data analytics device is able to keep pace with the data that is directed to the output, that data is used by the analytics device. If the analytics device is not able to keep pace, the data written to the data store is retrieved and is used until the analytics device has caught up.

公开(公告)号：US20230401480A1

公开(公告)日：2023-12-14

申请号：US17806906

申请日：2022-06-14

Applicant: Xilinx, Inc.

Inventor： Ehsan Ghasemi ,  Rajeev Patwari ,  Elliott Delaye ,  Jorn Tuyls ,  Ephrem C. Wu ,  Xiao Teng ,  Sanket Pandit

IPC: G06N20/00

CPC classification number: G06N20/00

Abstract: Hardware acceleration of machine learning (ML) designs includes translating an ML primitive into an intermediate representation. The intermediate representation is subdivided to specify a functional compute block. The functional compute block is sized according to a compute node primitive adapted for implementing the ML primitive on target hardware. An overlay is generated for the ML primitive, at least in part, by mapping the functional compute block to the compute node primitive. The overlay is synthesizable to implement the ML primitive on the target hardware. The overlay can be scheduled for operation within the target hardware as part of an ML design including the ML primitive.

公开(公告)号：US11836426B1

公开(公告)日：2023-12-05

申请号：US17819884

申请日：2022-08-15

Applicant: Xilinx, Inc.

Inventor： Fangqing Du ,  Alexandre Isoard ,  Lin-Ya Yu ,  Hem C. Neema

IPC: G06F30/327 ,  G06F15/80

CPC classification number: G06F30/327 ,  G06F15/80

Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.

公开(公告)号：US20230376437A1

公开(公告)日：2023-11-23

申请号：US17663824

申请日：2022-05-17

Applicant: Xilinx, Inc.

Inventor： David Patrick Clarke ,  Peter McColgan ,  Juan J. Noguera Serra ,  Tim Tuan ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Javier Cabezas Rodriguez ,  Pedro Miguel Parola Duarte ,  Zachary Blaise Dickman

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.

公开(公告)号：US11824830B2

公开(公告)日：2023-11-21

申请号：US17246310

申请日：2021-04-30

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

IPC: H04L29/06 ,  H04L9/40

CPC classification number: H04L63/0227 ,  H04L63/029

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

公开(公告)号：US11824534B2

公开(公告)日：2023-11-21

申请号：US17455195

申请日：2021-11-16

Applicant: XILINX, INC.

Inventor： Nakul Narang ,  Siok Wei Lim ,  Luhui Chen ,  Yipeng Wang ,  Kee Hian Tan

IPC: H04L25/02 ,  H03K19/17736 ,  G06F13/10 ,  H03K19/17788 ,  H04J3/04

CPC classification number: H03K19/17744 ,  G06F13/102 ,  H03K19/17788 ,  H04J3/047 ,  H04L25/0272

Abstract: A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.