公开(公告)号：US07855385B2

公开(公告)日：2010-12-21

申请号：US12152016

申请日：2008-05-12

申请人： Satoshi Kamiyama ,  Hiroshi Amano ,  Isamu Akasaki ,  Motoaki Iwaya ,  Masahiro Yoshimoto ,  Hiroyuki Kinoshita

发明人： Satoshi Kamiyama ,  Hiroshi Amano ,  Isamu Akasaki ,  Motoaki Iwaya ,  Masahiro Yoshimoto ,  Hiroyuki Kinoshita

IPC分类号： H01L31/0312

CPC分类号： B23K35/262 ,  C22C13/00 ,  H01B1/026

摘要： The present invention discloses a SiC crystal, comprising: acceptor impurities that are in a concentration greater than 5×1017 cm−3; donor impurities that are in a concentration less than 1×1019 cm−3 and greater than the concentration of the acceptor impurities. The present invention discloses a semiconductor device, comprising: a SiC fluorescent layer having acceptor impurities that are in a concentration greater than 5×1017 cm−3 and donor impurities that are in a concentration less than 1×1019 cm−3 and greater than the concentration of the acceptor impurities; and a light emission layer that is layered on the SiC fluorescent layer and emits excitation light for the SiC fluorescent layer.

摘要翻译： 本发明公开了一种SiC晶体，其包含：浓度大于5×1017cm-3的受主杂质; 供体杂质浓度小于1×1019 cm-3，大于受主杂质的浓度。 本发明公开了一种半导体器件，包括：具有浓度大于5×1017cm-3的受主杂质的SiC荧光层和浓度小于1×1019 cm -3并且大于 受体杂质浓度; 以及层叠在SiC荧光层上并发射用于SiC荧光层的激发光的发光层。

公开(公告)号：US07732826B2

公开(公告)日：2010-06-08

申请号：US11603977

申请日：2006-11-21

申请人： Satoshi Kamiyama ,  Hiroshi Amano ,  Isamu Akasaki ,  Motoaki Iwaya ,  Hiroyuki Kinoshita

发明人： Satoshi Kamiyama ,  Hiroshi Amano ,  Isamu Akasaki ,  Motoaki Iwaya ,  Hiroyuki Kinoshita

IPC分类号： H01L33/00

CPC分类号： H01L33/14 ,  H01L33/04 ,  H01L33/06 ,  H01L33/08 ,  H01L33/32

摘要： The present invention discloses a semiconductor, includes one or more luminescent layers; and one or more electron gas layers with two-dimensional electron gases that are distributed parallel to the luminescent layers.

摘要翻译： 本发明公开了一种半导体，包括一个或多个发光层; 以及具有与发光层平行分布的二维电子气体的一个或多个电子气体层。

公开(公告)号：US07576787B2

公开(公告)日：2009-08-18

申请号：US11499369

申请日：2006-08-04

申请人： Hiroyuki Kinoshita

发明人： Hiroyuki Kinoshita

IPC分类号： H04N9/64

CPC分类号： H04N5/367 ,  H04N2209/045

摘要： An image-pickup device includes a solid-image-pickup element which can select between an ordinary mode wherein all of a plurality of pixel signals are sequentially read and at least one pixel-addition mode wherein the pixel signals corresponding to same-color filters are added and output; a defective-information-storage unit which stores position information of a defective pixel on the solid-image-pickup element in the ordinary mode; a signal-correction unit which corrects a pixel signal of a picked-up-image signal based on the position information; and a position-information conversion unit that converts the position information when the pixel-addition mode is selected so that the position information agrees with information about a pixel arrangement, the pixel-arrangement information corresponding to the picked-up-image signal generated in the pixel-addition mode, and that transmits the converted position information to the signal-correction unit.

摘要翻译： 一种图像拾取装置包括可以在其中顺序读取所有多个像素信号的常规模式和至少一个像素相加模式之间进行选择的固体摄像元件，其中对应于相同滤色器的像素信号为 添加和输出; 缺陷信息存储单元，其以常规模式存储固体摄像元件上的缺陷像素的位置信息; 信号校正单元，其基于位置信息校正拾取图像信号的像素信号; 以及位置信息转换单元，其在选择像素相加模式时转换位置信息，使得位置信息与关于像素排列的信息一致，对应于在所述像素排列信息中生成的拍摄图像信号的像素排列信息 像素相加模式，并且将转换的位置信息发送到信号校正单元。

公开(公告)号：US20090111265A1

公开(公告)日：2009-04-30

申请号：US11924823

申请日：2007-10-26

申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC分类号： H01L21/4763

CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US20090061650A1

公开(公告)日：2009-03-05

申请号：US11847507

申请日：2007-08-30

申请人： Chungho Lee ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Huaqiang Wu ,  Fred Cheung

发明人： Chungho Lee ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Huaqiang Wu ,  Fred Cheung

IPC分类号： H01L21/31

CPC分类号： H01L21/28282 ,  H01L21/3185 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7923

摘要： Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

摘要翻译： 提供了在存储单元的电荷存储材料层周围形成顶部氧化物的方法以及提高存储单元的电荷存储材料层周围的顶部氧化物的质量的方法。 该方法可以包括在半导体衬底上提供电荷存储层，电荷存储层上的氮化物层和氮化物层上的第一多晶硅层，并将氮化物层的至少一部分转化为顶部氧化物。 通过将氮化物层的至少一部分转化为顶部氧化物层，可以提高所得顶部氧化物层的质量。

公开(公告)号：US20090033773A1

公开(公告)日：2009-02-05

申请号：US11665037

申请日：2006-08-09

申请人： Hiroyuki Kinoshita ,  Jing Zhang ,  Masahiro Ito ,  Akira Matsui

发明人： Hiroyuki Kinoshita ,  Jing Zhang ,  Masahiro Ito ,  Akira Matsui

IPC分类号： H04N5/217 ,  G06K9/40 ,  H04N5/00

CPC分类号： H04N5/21 ,  G06T3/4023 ,  G06T5/002 ,  G06T5/005 ,  G06T5/20 ,  G06T7/13 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20032 ,  G06T2207/20192 ,  H04N5/213

摘要： Noise reduction is performed on the basis of characteristics of an image in a detection range. A noise reduction block 4′ performs a second-order differentiation process and a symmetry process to decide adjacent pixels with which noise reduction is preformed for an attention pixel. With the pixel level of the attention pixel in the detection range and the pixel levels of adjacent pixels used for noise reduction, an arithmetic mean processing section 16 calculates a mean value. A median filter 17 selects a median value. With the number of pixels used for noise reduction, it is determined whether the image in the detection range contains a flat portion, a ramp portion, or an edge. The mean value and the median value are weight-added with a weighted coefficient that are changed on the basis of characteristics of the image. The result is substituted for the level of the attention pixel. When the attention pixel is an isolated point, an all-pixel median filter section 31 selects a medium value of the levels of all the pixels in the detection range including the attention pixel and substitutes the median value for the level of the attention pixel.

摘要翻译： 基于检测范围内的图像的特性进行降噪。 降噪块4'执行二阶微分处理和对称处理，以确定针对注意像素执行降噪的相邻像素。 利用检测范围内的关注像素的像素级和用于降噪的相邻像素的像素级，算术平均处理部16计算平均值。 中值滤波器17选择中值。 利用用于降噪的像素数量，确定检测范围内的图像是否包含平坦部分，斜坡部分或边缘。 平均值和中值是加权系数，加权系数根据图像的特性而改变。 结果代替注意像素的级别。 当注意像素是孤立点时，全像素中值滤波器部分31选择包括关注像素在内的检测范围内的所有像素的电平的中值，并代入关注像素的电平的中值。

公开(公告)号：US20080268650A1

公开(公告)日：2008-10-30

申请号：US11742003

申请日：2007-04-30

申请人： Chungho Lee ,  Huaqiang Wu ,  Wai Lo ,  Hiroyuki Kinoshita

发明人： Chungho Lee ,  Huaqiang Wu ,  Wai Lo ,  Hiroyuki Kinoshita

IPC分类号： H01L21/302

CPC分类号： H01L27/11573 ,  H01L21/28282

摘要： A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.

摘要翻译： 提供了替换存储器件的存储元件周围的顶部氧化物的方法。 该方法可以包括在核心区域中去除核心的第一多核和第一顶部氧化物，而不去除半导体衬底上的外围区域中的周边第一多晶硅; 在所述芯区域中的存储元件周围和所述周边区域的所述外围第一聚四氟乙烯上形成第二顶部氧化物; 在所述芯和外围区域中在所述半导体衬底上形成第二聚合物; 去除所述周边区域中的所述第二聚合物和第二顶部氧化物; 以及在所述芯和外围区域中在所述半导体衬底上形成第三聚合物。

公开(公告)号：US07242102B2

公开(公告)日：2007-07-10

申请号：US10887585

申请日：2004-07-08

申请人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon S Chan ,  Cinti X Chen

发明人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon S Chan ,  Cinti X Chen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042

摘要： According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

摘要翻译： 根据一个示例性实施例，半导体管芯中的结构包括位于互连金属层中的金属焊盘，其中金属焊盘包括铜。 该结构还包括位于金属焊盘上的层间电介质层。 该结构还包括限定在层间电介质层中的端子通孔，其中端子通孔位于金属焊盘上。 端子通孔仅沿着金属焊盘的一侧延伸。 该结构还包括位于层间电介质层和端子通孔中的端子金属层。 所述结构还包括位于所述端子金属层上的电介质衬垫，其中所述电介质衬垫中限定了焊盘开口，并且所述接合焊盘开口露出所述端子金属层的一部分。 层间绝缘层位于端子金属层的暴露部分和金属焊盘之间。

公开(公告)号：US07202540B2

公开(公告)日：2007-04-10

申请号：US11066567

申请日：2005-02-28

申请人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

发明人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/115 ,  H01L27/11568 ,  Y10S257/90

摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

摘要翻译： 漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并掺杂杂质的重掺杂深杂质区域（7b） 其浓度高于轻掺杂浅杂质区（7a）的浓度。 轻掺杂的浅杂质区域（7a）导致短沟道效应和编程效率的改善。 漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

公开(公告)号：US20060102924A1

公开(公告)日：2006-05-18

申请号：US10525753

申请日：2003-08-21

申请人： Shigeki Otani ,  Hiroyuki Kinoshita ,  Hiroyuki Matsunami ,  Jun Suda ,  Hiroshi Amano ,  Isamu Akasaki ,  Satoshi Kamiyama

发明人： Shigeki Otani ,  Hiroyuki Kinoshita ,  Hiroyuki Matsunami ,  Jun Suda ,  Hiroshi Amano ,  Isamu Akasaki ,  Satoshi Kamiyama

IPC分类号： H01L33/00

CPC分类号： H01L31/0264 ,  C30B29/10 ,  C30B33/00 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/24 ,  H01S5/0213 ,  H01S5/0218 ,  H01S5/32341

摘要： Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate 1 of diboride XB2 (where X is either Zr or Ti) which is facially oriented in a (0001) plane 2 and has a thickness of 0.1 mm or less. The substrate 1 is permitted cleaving and splitting along a (10-10) plane 4 with ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.

摘要翻译： 公开了具有与氮化物化合物半导体相同的解理面并具有导电性的二硼化物单晶基板; 半导体激光二极管和使用这种衬底的半导体器件及其制造方法，其中衬底是面向取向的二硼化物XB 2 N（其中X是Zr或Ti）的单晶衬底1 在（0001）面2中，具有0.1mm以下的厚度。 允许衬底1容易地沿着（10-10）平面4进行切割和分割。 使用该基板形成氮化物化合物的半导体激光二极管，可以实现垂直结构装置。 具有最小损耗的半导体激光二极管的谐振平面可以通过在与（10-10）平面平行的方向上分割器件来制造。 还实现了消除切割余量的制造方法。