利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

281 条记录 (耗时 0.045 秒)

    Aluminum/copper clad interconnect layer for VLSI applications
    61.
    发明授权
    Aluminum/copper clad interconnect layer for VLSI applications 有权

    公开(公告)号：US06777318B2

    公开(公告)日：2004-08-17

    申请号：US10222361

    申请日：2002-08-16

    申请人： Shin-Puu Jeng ,  Shang-Yun Hou

    发明人： Shin-Puu Jeng ,  Shang-Yun Hou

    IPC分类号： H01L2144

    CPC分类号： H01L23/53223 ,  H01L21/76838 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming at least one aluminum/copper clad interconnect comprising the following steps. A substrate is provided having an overlying patterned dielectric layer. The patterned dielectric layer having at least one lower opening. The at least one lower opening is lined with a first barrier layer. At least one planarized copper portion is formed within the at least one first barrier layer lined lower opening. A patterned layer is formed over the at least one planarized copper portion and the patterned dielectric layer. The patterned layer has at least one upper opening exposing at least a portion of the at least one planarized copper portion. The at least one upper opening is lined with a second barrier layer. At least one aluminum portion is formed within the at least one second barrier layer lined opening to form the at least one aluminum/copper clad interconnect.

    Through silicon via keep out zone formation along different crystal orientations
    64.
    发明授权
    Through silicon via keep out zone formation along different crystal orientations 有权
    通过硅通过沿着不同的晶体取向保持区域形成

    公开(公告)号：US08604619B2

    公开(公告)日：2013-12-10

    申请号：US13302653

    申请日：2011-11-22

    申请人： Cheng-Chieh Hsieh ,  Hung-An Teng ,  Shang-Yun Hou ,  Shin-Puu Jeng

    发明人： Cheng-Chieh Hsieh ,  Hung-An Teng ,  Shang-Yun Hou ,  Shin-Puu Jeng

    IPC分类号： H01L23/48

    CPC分类号： H01L23/562 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

    摘要翻译： 为硅通孔（TSV）形成保留区（KOZ）。 设备可以放置在由第一性能阈值确定的TSV的第一KOZ之外，使得由设备的TSV引起的应力冲击小于第一性能阈值，而第一KOZ仅包含应力冲击的那些点 由TSV引起的大于或等于第一个性能阈值。 用于TSV的第二KOZ可以类似地由第二性能阈值形成。 多个TSV可以沿着TSV的KOZ具有最小半径的方向被放置到TSV的中心，其可以是晶体取向[010]或[100]。 可以在多个TSV的整个KOZ的边界处形成多个TSV应力塞。

    Protective Seal Ring for Preventing Die-Saw Induced Stress
    68.
    发明申请
    Protective Seal Ring for Preventing Die-Saw Induced Stress 有权
    用于防止模切诱发应力的保护密封圈

    公开(公告)号：US20090321890A1

    公开(公告)日：2009-12-31

    申请号：US12347026

    申请日：2008-12-31

    申请人： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N.F. Wu ,  Yu-Wen Liu

    发明人： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N.F. Wu ,  Yu-Wen Liu

    IPC分类号： H01L23/10

    CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.

    摘要翻译： 半导体芯片包括半导体衬底; 半导体衬底上的多个低k电介质层; 在所述多个低k电介质层上的第一钝化层; 以及在所述第一钝化层上的第二钝化层。 第一密封环邻近半导体芯片的边缘，其中第一密封环具有基本上平坦于第一钝化层的底表面的上表面。 第二密封环与第一密封环相邻，并且在半导体芯片的内侧与第一密封环相邻。 第二密封环包括在第一钝化层和第二钝化层中的焊盘环。 沟槽环包括直接在第一密封环上的至少一部分。 沟槽环从第二钝化层的顶表面延伸到至少第一钝化层和第二钝化层之间的界面。

    Seal ring in semiconductor device
    69.
    发明授权
    Seal ring in semiconductor device 有权
    半导体器件中的密封环

    公开(公告)号：US07602065B2

    公开(公告)日：2009-10-13

    申请号：US12042573

    申请日：2008-03-05

    申请人： Shang-Yun Hou ,  Chun-Hung Chen ,  Chia-Lun Tsai ,  Pao-Kang Niu ,  Shin-Puu Jeng

    发明人： Shang-Yun Hou ,  Chun-Hung Chen ,  Chia-Lun Tsai ,  Pao-Kang Niu ,  Shin-Puu Jeng

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner opening is located on the inner side of the first seal ring. The outer opening is located on the outer side of the first seal ring. The outer opening and the inner opening are not aligned. The connecting groove connects the inner opening and the outer opening.

    摘要翻译： 半导体器件包括第一电路，第一密封环和至少一个第一凹口。 第一密封环围绕第一回路。 第一个切口切割第一个密封圈。 具体而言，第一凹口包括内部开口，外部开口和连接凹槽。 内部开口位于第一密封环的内侧。 外部开口位于第一密封环的外侧。 外部开口和内部开口未对齐。 连接槽连接内部开口和外部开口。

    Seal Ring Structure with Improved Cracking Protection
    70.
    发明申请
    Seal Ring Structure with Improved Cracking Protection 有权
    密封圈结构，提高破裂保护

    公开(公告)号：US20080283969A1

    公开(公告)日：2008-11-20

    申请号：US11842821

    申请日：2007-08-21

    申请人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

    发明人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

    IPC分类号： H01L23/00

    CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric layer; and a trench extending from a top surface of the first passivation layer into the first passivation layer, wherein the trench substantially forms a ring. Each side of the ring is adjacent to a respective edge of the semiconductor chip. At least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines.

    摘要翻译： 集成电路结构包括包括多个电介质层的半导体芯片，其中所述多个电介质层包括顶部电介质层; 以及与所述半导体芯片的边缘相邻的第一密封环。 集成电路结构还包括在顶部介电层上的第一钝化层; 以及从所述第一钝化层的顶表面延伸到所述第一钝化层中的沟槽，其中所述沟槽基本上形成环。 环的每一侧与半导体芯片的相应边缘相邻。 所述多个通孔中的至少一个具有大于所述多个金属线中相应的上覆金属线的宽度的约70％的宽度。