专利检索 ap:("Cheng-Chieh Hsieh" OR "Cheng-Lin Huang" OR "Po-Hao Tsai" OR "Shang-Yun Hou" OR "Jing-Cheng Lin" OR "Shin-Puu Jeng") AND inv:"Jing-Cheng Lin" 第 1 页

1.

发明申请
Pillar Design for Conductive Bump 审中-公开
标题翻译：导柱凸块支柱设计

公开(公告)号：US20130020698A1

公开(公告)日：2013-01-24

申请号：US13189127

申请日：2011-07-22

申请人： Cheng-Chieh Hsieh , Cheng-Lin Huang , Po-Hao Tsai , Shang-Yun Hou , Jing-Cheng Lin , Shin-Puu Jeng

发明人： Cheng-Chieh Hsieh , Cheng-Lin Huang , Po-Hao Tsai , Shang-Yun Hou , Jing-Cheng Lin , Shin-Puu Jeng

IPC分类号： H01L23/485 , H01L21/768

CPC分类号： H01L24/81 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/1132 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11474 , H01L2224/1148 , H01L2224/11616 , H01L2224/11825 , H01L2224/11849 , H01L2224/1191 , H01L2224/13013 , H01L2224/13015 , H01L2224/13018 , H01L2224/13019 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1362 , H01L2224/13655 , H01L2224/13671 , H01L2224/13672 , H01L2224/16056 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/81121 , H01L2224/81143 , H01L2224/81193 , H01L2224/81815 , H01L2225/06513 , H01L2225/06555 , H01L2225/06565 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/12 , H01L2924/14 , H01L2924/3512 , H01L2924/35121 , H01L2924/384 , H01L2924/3841 , H01L2924/00014

摘要： A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

摘要翻译： 提供了一种用于导电柱的系统和方法。一个实施例包括具有位于其外边缘周围的沟槽的导电柱。当在导电柱上形成导电凸块时，沟槽用于引导诸如焊料的导电材料。导电柱然后可以通过导电材料电连接到另一接触件。

2.

发明申请
Packaging Structures and Methods 有权
标题翻译：包装结构与方法

公开(公告)号：US20120306080A1

公开(公告)日：2012-12-06

申请号：US13298046

申请日：2011-11-16

申请人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Kuo-Ching Hsu , Cheng-Chieh Hsieh , Ying-Ching Shih , Po-Hao Tsai , Cheng-Lin Huang , Jing-Cheng Lin

发明人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Kuo-Ching Hsu , Cheng-Chieh Hsieh , Ying-Ching Shih , Po-Hao Tsai , Cheng-Lin Huang , Jing-Cheng Lin

IPC分类号： H01L23/52

CPC分类号： H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00

摘要： A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

摘要翻译： 封装组件不含其中的有源器件。封装部件包括衬底，衬底中的通孔，衬底上的顶部电介质层和在顶部电介质层的顶表面上方具有顶表面的金属柱。金属柱电连接到通孔。扩散阻挡层在金属支柱的上表面之上。焊料帽设置在扩散阻挡层上。

3.

发明授权
Pillar design for conductive bump 有权

公开(公告)号：US08816498B2

公开(公告)日：2014-08-26

申请号：US13189127

申请日：2011-07-22

申请人： Cheng-Chieh Hsieh , Cheng-Lin Huang , Po-Hao Tsai , Shang-Yun Hou , Jing-Cheng Lin , Shin-Puu Jeng

发明人： Cheng-Chieh Hsieh , Cheng-Lin Huang , Po-Hao Tsai , Shang-Yun Hou , Jing-Cheng Lin , Shin-Puu Jeng

IPC分类号： H01L23/485 , H01L21/768

摘要： A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

4.

发明授权
Connector design for packaging integrated circuits 有权

公开(公告)号：US08664760B2

公开(公告)日：2014-03-04

申请号：US13343582

申请日：2012-01-04

申请人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin

发明人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin

IPC分类号： H01L23/48 , H01L23/52 , H01L29/40

CPC分类号： H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00

摘要： A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

5.

发明授权
3D IC packaging structures and methods with a metal pillar 有权
标题翻译： 3D IC封装结构和方法与金属支柱

公开(公告)号：US08610285B2

公开(公告)日：2013-12-17

申请号：US13298046

申请日：2011-11-16

申请人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Kuo-Ching Hsu , Cheng-Chieh Hsieh , Ying-Ching Shih , Po-Hao Tsai , Cheng-Lin Huang , Jing-Cheng Lin

发明人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Kuo-Ching Hsu , Cheng-Chieh Hsieh , Ying-Ching Shih , Po-Hao Tsai , Cheng-Lin Huang , Jing-Cheng Lin

IPC分类号： H01L23/498 , H01L21/768 , H01L23/48 , H01L29/40

CPC分类号： H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00

摘要： A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

摘要翻译： 封装组件不含其中的有源器件。封装部件包括衬底，衬底中的通孔，衬底上的顶部电介质层，以及在顶部电介质层的顶表面上方具有顶表面的金属柱。金属柱电连接到通孔。扩散阻挡层在金属支柱的上表面之上。焊料帽设置在扩散阻挡层上。

6.

发明申请
Connector Design for Packaging Integrated Circuits 有权
标题翻译：封装集成电路连接器设计

公开(公告)号：US20120306073A1

公开(公告)日：2012-12-06

申请号：US13343582

申请日：2012-01-04

申请人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin

发明人： Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin

IPC分类号： H01L23/485 , H01L21/768

CPC分类号： H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00

摘要： A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

摘要翻译： 一种器件包括具有顶表面的顶部电介质层。金属柱在顶部介电层的顶表面上具有一部分。在金属柱的侧壁上形成非润湿层，其中非润湿层不能熔化到熔融焊料上。焊接区域设置在金属柱上并电耦合到金属柱。

7.

发明授权
Self-aligning conductive bump structure and method of making the same 有权
标题翻译：自对准导电凸块结构及其制造方法

公开(公告)号：US09024438B2

公开(公告)日：2015-05-05

申请号：US13192756

申请日：2011-07-28

申请人： Cheng-Lin Huang , I-Ting Chen , Ying Ching Shih , Po-Hao Tsai , Szu Wei Lu , Jing-Cheng Lin , Shin-Puu Jeng , Chen-Hua Yu

发明人： Cheng-Lin Huang , I-Ting Chen , Ying Ching Shih , Po-Hao Tsai , Szu Wei Lu , Jing-Cheng Lin , Shin-Puu Jeng , Chen-Hua Yu

IPC分类号： H01L23/498 , H01L21/60 , H01L23/00

CPC分类号： H01L24/14 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/17 , H01L24/81 , H01L2224/0346 , H01L2224/03912 , H01L2224/0401 , H01L2224/1146 , H01L2224/11462 , H01L2224/11472 , H01L2224/1161 , H01L2224/11622 , H01L2224/13011 , H01L2224/13014 , H01L2224/13078 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/1405 , H01L2224/14051 , H01L2224/145 , H01L2224/16238 , H01L2224/17107 , H01L2224/81141 , H01L2224/81193 , H01L2224/81815 , H01L2224/81897 , H01L2924/1305 , H01L2924/1306 , H01L2924/00014 , H01L2924/01047 , H01L2924/01082 , H01L2924/01029 , H01L2924/0103 , H01L2924/01083 , H01L2924/01053 , H01L2924/01079 , H01L2924/01051 , H01L2924/014 , H01L2924/00012 , H01L2924/00

摘要： A conductive bump structure of a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprises a regular body, and each of a second subset of the conductive bumps comprises a ring-shaped body.

摘要翻译： 半导体器件的导电凸块结构包括包括主表面的衬底和分布在衬底的主表面上的导电凸块。导电凸块的第一子集中的每一个包括规则体，并且导电凸块的第二子集中的每一个包括环形体。

8.

发明授权
Approach for bonding dies onto interposers 有权
标题翻译：将模具接合到插入件上

公开(公告)号：US08105875B1

公开(公告)日：2012-01-31

申请号：US12904835

申请日：2010-10-14

申请人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu

发明人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu

IPC分类号： H01L21/50

CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。多个管芯结合到插入件晶片的前表面上。在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

9.

发明授权
Approach for bonding dies onto interposers 有权

公开(公告)号：US08319349B2

公开(公告)日：2012-11-27

申请号：US13342583

申请日：2012-01-03

申请人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu

发明人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu

IPC分类号： H01L23/48

CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

10.

发明授权
Approach for bonding dies onto interposers 有权
标题翻译：将模具接合到插入件上

公开(公告)号：US08759150B2

公开(公告)日：2014-06-24

申请号：US13488188

申请日：2012-06-04

申请人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu

发明人： Hsien-Pin Hu , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu

IPC分类号： H01L21/50

CPC分类号： H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。多个管芯结合到插入件晶片的前表面上。在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

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