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    FINFET SEMICONDUCTOR DEVICES WITH STRESSED CHANNEL REGIONS
    64.
    发明申请
    FINFET SEMICONDUCTOR DEVICES WITH STRESSED CHANNEL REGIONS 审中-公开
    FINFET半导体器件与应力通道区域

    公开(公告)号：US20160293706A1

    公开(公告)日：2016-10-06

    申请号：US15186632

    申请日：2016-06-20

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

    IPC: H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78

    CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

    Abstract: A FinFET device includes a substrate, a gate structure positioned above the substrate, and sidewall spacers positioned adjacent to the gate structure. An epi semiconductor material is positioned in source and drain regions of the FinFET device and laterally outside of the sidewall spacers. A fin extends laterally under the gate structure and the sidewall spacers in a gate length direction of the FinFET device, wherein the end surfaces of the fin abut and engage the epi semiconductor material. A stressed material is positioned in a channel cavity located below the fin, above the substrate, and laterally between the epi semiconductor material, the stressed material having a top surface that abuts and engages a bottom surface of the fin, a bottom surface that abuts and engages the substrate, and end surfaces that abut and engage the epi semiconductor material.

    Abstract translation: FinFET器件包括衬底，位于衬底上方的栅极结构以及邻近栅极结构定位的侧壁间隔物。 外延半导体材料位于FinFET器件的源极和漏极区域中，并且横向在侧壁间隔物的外侧。 翅片在FinFET器件的栅极长度方向上在栅极结构和侧壁间隔物之下横向延伸，其中鳍片的端面抵靠并接合外延半导体材料。 应力材料定位在位于翅片下方的衬底上方的通道腔中，并且横向地位于外延半导体材料之间，受压材料具有邻接并接合翅片的底表面的顶表面，邻接的底表面和 接合基板以及邻接和接合外延半导体材料的端面。

    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME
    66.
    发明申请
    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME 有权
    用于集成电路晶体管器件的引出源漏极触点及其制造方法

    公开(公告)号：US20160284599A1

    公开(公告)日：2016-09-29

    申请号：US15179620

    申请日：2016-06-10

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

    Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

    IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/84

    CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

    Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地被金属材料填充以形成埋在衬底中的源极（或漏极）触点。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

    Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
    67.
    发明授权
    Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices 有权
    使用替代栅极技术形成用于半导体器件的栅极结构的方法和所得到的器件

    公开(公告)号：US09437711B2

    公开(公告)日：2016-09-06

    申请号：US14081019

    申请日：2013-11-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiuyu Cai ,  Xunyuan Zhang

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: One method disclosed herein includes, among other things, performing a process operation on an exposed surface of a substrate so as to form an H-terminated silicon surface, selectively forming a sacrificial material layer within a replacement gate cavity but not on the H-terminated silicon surface, forming a high-k layer of insulating material within the replacement gate cavity above the H-terminated silicon surface and laterally between first spaced-apart portions of the sacrificial material layer, and forming a work-function adjusting material layer in the gate cavity, wherein the work-function adjusting material layer has a substantially planar upper surface that extends between second spaced-apart portions of the sacrificial material layer formed on the sidewall spacers.

    Abstract translation: 本文公开的一种方法包括在衬底的暴露表面上执行处理操作以形成H端接的硅表面，在置换栅腔内选择性地形成牺牲材料层，但不在H端接 硅表面，在H端接的硅表面上方的置换栅腔内形成高k层绝缘材料，并在牺牲材料层的第一间隔开的部分之间横向地形成绝缘材料的高k层，并在栅极中形成功函数调节材料层 空腔，其中所述功函调整材料层具有在形成在所述侧壁间隔物上的所述牺牲材料层的第二间隔开的部分之间延伸的基本平坦的上表面。

    Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
    68.
    发明授权
    Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same 有权
    集成电路包括具有较低接触电阻和降低的寄生电容的FINFET器件及其制造方法

    公开(公告)号：US09425319B2

    公开(公告)日：2016-08-23

    申请号：US14551606

    申请日：2014-11-24

    Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8234

    CPC classification number: H01L29/7853 ,  H01L21/28 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，集成电路包括半导体衬底。 第一翅片和第二翅片彼此相邻，从半导体衬底延伸。 第一翅片具有第一上部，第二翅片具有第二上部。 第一外延部分覆盖第一上部，第二外延部分覆盖第二上部。 第一硅化物层覆盖第一外延部分，第二硅化物层覆盖第二外延部分。 第一和第二硅化物层彼此间隔开以限定横向间隙。 电介质隔离物由电介质材料形成并横跨横向间隙。 接触形成材料覆盖介质间隔物和第一和第二硅化物层的在电介质间隔物的横向上方的部分。

    Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
    69.
    发明授权
    Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device 有权
    形成用于FinFET半导体器件的应力沟道区域的方法和所得到的器件

    公开(公告)号：US09412822B2

    公开(公告)日：2016-08-09

    申请号：US14200737

    申请日：2014-03-07

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

    IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06

    CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

    Abstract: One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material.

    Abstract translation: 所公开的一种方法包括用蚀刻停止材料覆盖初始翅片结构的顶表面和侧壁的一部分，围绕初始翅片结构形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物， 去除牺牲栅极结构，其中蚀刻停止材料就位，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺，以移除位于替换下方的鳍结构的半导体衬底材料的一部分 门腔不被蚀刻停止材料覆盖，从而限定最终的翅片结构和位于最终翅片结构下方的通道腔，并且用应力材料基本上填充通道腔。

    Method for making semiconductor device with different fin sets
    70.
    发明授权
    Method for making semiconductor device with different fin sets 有权
    制造具有不同翅片组的半导体器件的方法

    公开(公告)号：US09299721B2

    公开(公告)日：2016-03-29

    申请号：US14280998

    申请日：2014-05-19

    Applicant: STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

    IPC: H01L21/30 ,  H01L27/12 ,  H01L29/66

    CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

    Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

    Abstract translation: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物，以及在第二半导体区域上方并邻近间隔物形成第三半导体区域，其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分，从第一半导体区域形成第一组散热片，以及从第二和第三半导体区域形成第二组散热片。

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