公开(公告)号：US09435948B2

公开(公告)日：2016-09-06

申请号：US14304318

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert K. Leidy ,  Mark D. Levy ,  Qizhi Liu ,  Gary L. Milo ,  Steven M. Shank

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/125 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12061

Abstract: Various embodiments include a silicon-based optical waveguide structure locally on a bulk silicon substrate, and systems and program products for forming such a structure by modifying an integrated circuit (IC) design structure. Embodiments include implementing processes of preparing manufacturing data for formation of the IC design structure in a computer-implemented IC formation system, wherein the preparing of the manufacturing data includes inserting instructions into the manufacturing data to convert an edge of the at least one shape from a crystallographic direction to a crystallographic direction.

Abstract translation: 各种实施例包括局部在体硅衬底上的硅基光波导结构，以及用于通过修改集成电路（IC）设计结构来形成这种结构的系统和程序产品。 实施例包括实现在计算机实现的IC形成系统中准备用于形成IC设计结构的制造数据的过程，其中制造数据的准备包括将指令插入到制造数据中以将至少一种形状的边缘从 <110>结晶方向到<100>晶体方向。

公开(公告)号：US20160225917A1

公开(公告)日：2016-08-04

申请号：US15092976

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： James W. Adkisson ,  James S. Dunn ,  Blaine J. Gross ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/808 ,  G06F17/50 ,  H01L29/161 ,  H01L29/06 ,  H01L29/47

CPC classification number: H01L29/808 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  H01L21/28026 ,  H01L21/306 ,  H01L21/8232 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66901 ,  H01L29/66924 ,  H01L29/7782 ,  H01L29/8124

Abstract: At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

公开(公告)号：US09349845B2

公开(公告)日：2016-05-24

申请号：US14495057

申请日：2014-09-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： David L. Harame ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/735 ,  H01L29/732 ,  H01L29/06 ,  H01L29/10 ,  H01L27/082 ,  H01L29/73 ,  G06F17/50

CPC classification number: H01L29/735 ,  G06F17/5045 ,  H01L27/0823 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732

Abstract: Device structures and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 在基板上形成本征基底，在本征基底上形成端子，并且形成与本征基底并列布置在基底上的非本征基底。 本征基极和端子分别由第一和第二半导体材料构成。

公开(公告)号：US09312370B2

公开(公告)日：2016-04-12

申请号：US14300944

申请日：2014-06-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  David L. Harame ,  Michael L. Kerbaugh ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/73 ,  H01L29/732 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/732 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7327 ,  H01L29/7371 ,  H01L29/7378

Abstract: The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.

Abstract translation: 本公开涉及集成电路（IC）结构及其形成方法。 根据本公开的IC结构可以包括：与绝缘区域相邻的掺杂衬底区域; 晶体基底结构，其包括：位于掺杂衬底区域上并与其接触的本征基极区域，本征基极区域具有第一厚度; 与所述绝缘区域相邻的外部基极区域，其中所述非本征基极区域具有大于所述第一厚度的第二厚度; 位于所述晶体基底结构的本征基极区上的半导体层; 以及位于半导体层上的掺杂半导体层。

公开(公告)号：US09276002B2

公开(公告)日：2016-03-01

申请号：US14734310

申请日：2015-06-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Qizhi Liu ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/10826 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. An IC structure according to the present disclosure can include: a bulk substrate; a finFET located on a first region of the bulk substrate; and a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes a first crystalline semiconductive layer, a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer, and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer.

Abstract translation: 本公开通常提供具有体硅片finFET的集成电路（IC）结构及其形成方法。 根据本公开的IC结构可以包括：体基板; 位于所述本体衬底的第一区域上的鳍状物FET; 以及分层虚拟结构，其位于所述本体衬底的第二区域上，其中所述分层虚拟结构包括第一晶体半导体层，位于所述第一晶体半导体层上的第二晶体半导体层，其中所述第一晶体半导体层包括不同的材料 以及位于所述第二晶体半导体层上的第三晶体半导体层，其中所述第三晶体半导体层包括与所述第二晶体半导体层不同的材料。