公开(公告)号：US10056377B2

公开(公告)日：2018-08-21

申请号：US15786164

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Bipul C. Paul

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L23/528 ,  H01L29/78

Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

公开(公告)号：US09960086B2

公开(公告)日：2018-05-01

申请号：US15274974

申请日：2016-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mira Park ,  Kwan-Yong Lim ,  Steven Bentley ,  Amitabh Jain

IPC: H01L21/31 ,  H01L21/82 ,  H01L21/30 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/223 ,  H01L21/324

CPC classification number: H01L21/823892 ,  H01L21/2236 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.

公开(公告)号：US09947804B1

公开(公告)日：2018-04-17

申请号：US15657659

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Steven Bentley

IPC: H01L21/84 ,  H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/78696 ,  H01L21/823412 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66431 ,  H01L29/775 ,  H01L29/778

Abstract: An IC structure according to the disclosure includes: a substrate; a pair of transistor sites positioned on the substrate, wherein an upper surface of the substrate laterally between the pair of transistor sites defines a separation region; a pair of nanosheet stacks, each positioned on one of the pair of transistor sites; an insulative liner conformally positioned on the upper surface of the substrate within the separation region, and a sidewall surface of each of the pair of transistor sites; a semiconductor mandrel positioned on the insulative liner and over the separation region; a pair of insulator regions each positioned laterally between the semiconductor mandrel and the insulative liner on the sidewall surfaces of each of the pair of transistor sites; and a source/drain epitaxial region positioned over the pair of insulator regions and the semiconductor mandrel, wherein the source/drain epitaxial region laterally abuts the pair of nanosheet stacks.

公开(公告)号：US09865682B2

公开(公告)日：2018-01-09

申请号：US14476918

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

公开(公告)号：US20170250250A1

公开(公告)日：2017-08-31

申请号：US15056966

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Deepak Nayak

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02532 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

公开(公告)号：US09647086B2

公开(公告)日：2017-05-09

申请号：US14826803

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporations ,  STMicroelectronics, Inc.

Inventor： Steven Bentley ,  Jody Fronheiser ,  Xin Miao ,  Joseph Washington ,  Pierre Morin

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L29/66537 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

公开(公告)号：US09613817B1

公开(公告)日：2017-04-04

申请号：US15138311

申请日：2016-04-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Vimal Kamineni

IPC: H01L21/285 ,  H01L21/8238

CPC classification number: H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871

Abstract: A method of enhancing surface diffusion species concentration in source/drain regions includes providing a substrate for an integrated circuit. One of an n-type and a p-type S/D region for a semiconductor device is formed on a surface of the substrate. A top surface of the S/D region is exposed. A diffusion layer is deposited over the top surface of the S/D region, the diffusion layer having a concentration of a diffusion species. The diffusion layer is heated to diffuse the diffusion species into the S/D region to enhance a concentration of the diffusion species proximate the top surface of the S/D region. The diffusion layer is removed from the top surface of the S/D region. A metal layer is deposited over the top surface of the S/D region immediately after removing the diffusion layer. Electrical contacts are formed over the top surface of the S/D region from the metal layer.

公开(公告)号：US09577042B1

公开(公告)日：2017-02-21

申请号：US14825949

申请日：2015-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Rohit Galatage

IPC: H01L29/205 ,  H01L29/165 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.

Abstract translation: 完全III-V半导体或Si基晶体管的源极/漏极包括可以与沟道晶格匹配的底部阻挡层，宽带隙III-V材料的下层和较窄带隙的顶层 III-V材料，下层和顶层之间的组成渐变层从宽带隙材料逐渐过渡到窄带隙材料。

公开(公告)号：US20160268399A1

公开(公告)日：2016-09-15

申请号：US14643409

申请日：2015-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Steven Bentley

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.

Abstract translation: 本文公开的一种说明性方法包括在器件的源极/漏极区域中形成绝缘材料层，其中绝缘材料层具有与栅极盖层的上表面基本上平面的上表面 使绝缘材料层凹陷，使得其凹陷的上表面暴露在鳍片的表面上，执行另一蚀刻工艺以移除鳍片的至少一部分，从而限定位于凹鳍片上方的凹陷散热片沟槽，并形成外延 所述半导体材料至少部分地位于所述凹陷散热片沟槽中。

公开(公告)号：US09299775B2

公开(公告)日：2016-03-29

申请号：US14254866

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Steven Bentley ,  Kejia Wang ,  Sylvie Mignot ,  Shurong Liang

IPC: H01L21/76 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02057 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/76224 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases.

Abstract translation: 提供了用于制造这种集成电路的集成电路和方法。 一种用于制造集成电路的方法包括在衬底中形成虚拟结构，以及在虚设结构之间形成浅沟槽隔离区，其中浅沟槽隔离区包括覆盖在芯上的衬垫。 蚀刻虚拟结构以暴露结构基底，并且将结构基底预清洁。 替代结构在结构基底上外延生长。