公开(公告)号：US20170330790A1

公开(公告)日：2017-11-16

申请号：US15152797

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L21/84 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/66 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02271 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/66 ,  H01L27/1248 ,  H01L29/78654

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

公开(公告)号：US09818637B2

公开(公告)日：2017-11-14

申请号：US14982576

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US20170309573A1

公开(公告)日：2017-10-26

申请号：US15646325

申请日：2017-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Baozhen Li

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257

Abstract: Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.

公开(公告)号：US09758365B2

公开(公告)日：2017-09-12

申请号：US14821997

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David L. Harame ,  Anthony K. Stamper

IPC: H01L29/84 ,  B81B3/00 ,  H01L21/84 ,  H01L27/12 ,  H03H3/02 ,  H03H9/10 ,  H03H9/17 ,  H01L41/113 ,  H03H1/00 ,  H03H9/24 ,  H03H9/15

CPC classification number: B81B3/0027 ,  B81B2201/0285 ,  H01L21/84 ,  H01L27/1203 ,  H01L41/1136 ,  H01L2224/73265 ,  H03H3/02 ,  H03H9/1007 ,  H03H9/173 ,  H03H2001/0064 ,  H03H2003/027 ,  H03H2009/155 ,  H03H2009/241

Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material exposing a wafer underlying the insulator. The insulator material remains over the single crystalline beam. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity above the single crystalline beam and a lower cavity in the wafer, below the single crystalline beam.

公开(公告)号：US20170162656A1

公开(公告)日：2017-06-08

申请号：US14959825

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/267 ,  H01L25/00 ,  H01L29/737 ,  H01L29/161 ,  H01L27/092 ,  H01L25/065 ,  H01L29/20

CPC classification number: H01L29/267 ,  H01L21/8258 ,  H01L23/3114 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/737 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2224/83

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.

公开(公告)号：US09461017B1

公开(公告)日：2016-10-04

申请号：US14685061

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Andrew H. Simon ,  Anthony K. Stamper

IPC: H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/66 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/66 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/8112 ,  H01L2224/8312 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14

Abstract: An electronic package comprising a plurality of vertically stacked integrated circuit (IC) devices including a first IC device and a second IC device is provided. The electronic package also includes a first bonding layer coupling one side of the first IC device entirely to a portion of a side of the second IC device. The remaining portion of the side of the second IC device that is not coupled to the one side of the first IC device, includes an antenna.

Abstract translation: 提供了一种包括多个垂直堆叠集成电路（IC）装置的电子封装，包括第一IC器件和第二IC器件。 电子封装还包括将第一IC器件的一侧完全耦合到第二IC器件的一侧的一部分的第一接合层。 第二IC器件的未耦合到第一IC器件的一侧的侧面的剩余部分包括天线。

公开(公告)号：US09385179B2

公开(公告)日：2016-07-05

申请号：US13765105

申请日：2013-02-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  H01L29/66

CPC classification number: H01L28/40 ,  H01L29/66181 ,  H01L29/945

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer.

Abstract translation: 公开了用于形成硅化深沟槽去耦电容器的解决方案。 一方面，一种形成半导体器件的方法包括：在硅衬底中形成外部沟槽，所述硅衬底的所述成形暴露部分位于所述硅衬底的上表面下方; 在沟槽内沉积介电衬垫层; 在所述介​​质衬底层上沉积掺杂多晶硅层，所述掺杂多晶硅层在所述硅衬底中形成内部沟槽; 在所述掺杂多晶硅层的一部分上形成硅化物层; 在所述内沟槽内形成中间接触层; 以及在所述中间接触层的一部分和所述硅化物层的一部分上形成接触。

公开(公告)号：US20160087073A1

公开(公告)日：2016-03-24

申请号：US14958345

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Inc

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/66242 ,  H01L29/0649 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.

公开(公告)号：US09231074B2

公开(公告)日：2016-01-05

申请号：US13946379

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Anthony K. Stamper

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66242 ,  H01L29/0649 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.

Abstract translation: 双极结型晶体管的器件结构，制造方法和设计结构。 在衬底中形成沟槽隔离区。 沟槽隔离区域与衬底中的集电极共同延伸。 基底层形成在集电器和沟槽隔离区的第一部分上。 电介质层形成在基底层上和在基底层周边的沟槽隔离区域的第二部分上。 在形成电介质层之后，至少部分去除沟槽隔离区域以在电介质层和基底层下方形成气隙。

公开(公告)号：US20210057462A1

公开(公告)日：2021-02-25

申请号：US16544074

申请日：2019-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L27/144 ,  H01L29/04 ,  H01L29/165 ,  H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L31/0312 ,  H01L31/02 ,  H01L31/105 ,  H01L31/18

Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.