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    STORAGE CELL HAVING A T-SHAPED GATE ELECTRODE AND METHOD FOR MANUFACTURING THE SAME
    62.
    发明申请
    STORAGE CELL HAVING A T-SHAPED GATE ELECTRODE AND METHOD FOR MANUFACTURING THE SAME 有权
    具有T形门电极的存储单元及其制造方法

    公开(公告)号：US20090294825A1

    公开(公告)日：2009-12-03

    申请号：US12131794

    申请日：2008-06-02

    申请人： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

    发明人： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/11517 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

    摘要翻译： 提供了一种用于制造包括至少一个存储单元的集成电路的方法。 该方法包括提供具有第一和第二侧面以及多个平行沟槽的衬底，使得在相邻沟槽之间形成分隔壁，用绝缘化合物填充沟槽，从而提供第一和第二侧面的第一绝缘层 分隔壁的上表面，其中第一侧布置在基板的第一侧上，提供具有第一和第二侧的第一导电层，其中第一侧布置在绝缘层的第二侧上，其中导电层突出 从基板表面提供具有第一和第二侧面的第二导电层，其中第一侧位于第一导电层的第二侧上，并通过各向异性蚀刻装置去除第二导电层的部分。

    Memory array having an interconnect and method of manufacture
    64.
    发明申请
    Memory array having an interconnect and method of manufacture 审中-公开
    具有互连和制造方法的存储器阵列

    公开(公告)号：US20080074927A1

    公开(公告)日：2008-03-27

    申请号：US11525547

    申请日：2006-09-22

    申请人： Franz Hofmann ,  Michael Specht ,  Nicolas Nagel ,  Josef Willer

    发明人： Franz Hofmann ,  Michael Specht ,  Nicolas Nagel ,  Josef Willer

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A memory array includes first, second, third and forth memory cell strings. Each of the first, second, third, and fourth memory cell strings includes a number of serially-coupled memory cells, including a first memory cell and a last memory cell. A first interconnect is coupled to a first bit line and to each of the first, second, third and fourth memory cell strings. The first interconnect includes first, second, third and fourth string input select gates. Each input select gate has a first terminal coupled to the first bit line, and a second terminal coupled to one of the respective first, second, third or fourth memory cell strings.

    摘要翻译： 存储器阵列包括第一，第二，第三和第四存储器单元串。 第一，第二，第三和第四存储器单元串中的每一个包括多个串行耦合的存储器单元，包括第一存储单元和最后存储单元。 第一互连耦合到第一位线和第一，第二，第三和第四存储器单元串中的每一个。 第一互连包括第一，第二，第三和第四串输入选择门。 每个输入选择栅极具有耦合到第一位线的第一端子和耦合到相应的第一，第二，第三或第四存储器单元串之一的第二端子。

    Memory cell arrangements and methods of manufacturing memory cell arrangements
    65.
    发明申请
    Memory cell arrangements and methods of manufacturing memory cell arrangements 有权
    存储单元布置和制造存储单元布置的方法

    公开(公告)号：US20080073694A1

    公开(公告)日：2008-03-27

    申请号：US11526149

    申请日：2006-09-22

    申请人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    发明人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    IPC分类号： H01L29/788

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

    摘要翻译： 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管 晶体管，其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。

    SEMICONDUCTOR DEVICE
    66.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20060102941A1

    公开(公告)日：2006-05-18

    申请号：US10986060

    申请日：2004-11-12

    申请人： Hiroshi Itokawa ,  Koji Yamakawa ,  Tohru Ozaki ,  Yoshinori Kumura ,  Takamichi Tsuchiya ,  Nicolas Nagel ,  Bum-Ki Moon ,  Andreas Hilliger

    发明人： Hiroshi Itokawa ,  Koji Yamakawa ,  Tohru Ozaki ,  Yoshinori Kumura ,  Takamichi Tsuchiya ,  Nicolas Nagel ,  Bum-Ki Moon ,  Andreas Hilliger

    IPC分类号： H01L29/94

    CPC分类号： H01L28/55 ,  G11C11/22 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

    摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

    摘要翻译： 公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方并包括底电极，顶电极和设置在底电极和顶电极之间的电介质膜的电容器，底电极包括含有 铱，设置在电介质膜和第一导电膜之间并由贵金属膜形成的第二导电膜，设置在电介质膜和第二导电膜之间并由具有钙钛矿结构的金属氧化物膜形成的第三导电膜， 以及设置在所述第一导电膜和所述第二导电膜之间并且包括金属膜和金属氧化物膜中的至少一种的防扩散膜，所述扩散防止膜防止包含在所述第一导电膜中的铱的扩散。

    Memory cells with improved reliability
    68.
    发明授权
    Memory cells with improved reliability 有权
    具有提高可靠性的存储单元

    公开(公告)号：US06621683B1

    公开(公告)日：2003-09-16

    申请号：US10065127

    申请日：2002-09-19

    申请人： Bum-ki Moon ,  Andreas Hilliger ,  Nicolas Nagel ,  Gerhard Beitel

    发明人： Bum-ki Moon ,  Andreas Hilliger ,  Nicolas Nagel ,  Gerhard Beitel

    IPC分类号： H01G4228

    CPC分类号： H01L27/11502 ,  H01L21/76895 ,  H01L27/11507 ,  H01L28/60

    摘要： A capacitor with improved reliability is disclosed. The capacitor includes a bottom electrode, a top electrode, and an intermediate layer therebetween. A contact, which is electrically coupled to the top electrode, is provided. At least a portion of the contact is offset from the capacitor. By offsetting the contact from the top electrode, the etch damage to the top electrode is reduced, thereby reducing or eliminating the need for the anneal to repair the etch damage.

    摘要翻译： 公开了具有可靠性提高的电容器。 电容器包括底部电极，顶部电极和它们之间的中间层。 提供了电耦合到顶部电极的触点。 触点的至少一部分偏离电容器。 通过抵消与顶部电极的接触，对顶部电极的蚀刻损伤减小，从而减少或消除了退火以修复蚀刻损伤的需要。