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61.发明授权公开(公告)号：US08580646B2
公开(公告)日：2013-11-12
申请号：US12948805
申请日：2010-11-18
IPC分类号： H01L21/336 , H01L21/331 , H01L21/425 , H01L21/26 , H01L21/42
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/268 , H01L29/665
摘要： Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.
摘要翻译： 场效应晶体管和形成场效应晶体管的方法。 场效应晶体管包括：半导体衬底中的沟道区上的栅极电介质; 栅电极上的栅电极; 在沟道区域的相对侧上的衬底中的相应源极/漏极; 靠近源极/漏极的栅电极的相对侧上的侧壁间隔物; 并且其中所述侧壁间隔物包括介电常数低于二氧化硅的介电常数且能够吸收激光辐射的材料。
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公开(公告)号：US08518767B2
公开(公告)日：2013-08-27
申请号：US11680221
申请日：2007-02-28
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66818
摘要： Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.
摘要翻译： 本发明的实施例提供了Fin场效应晶体管（FinFET）中的相对均匀的宽度鳍片及其形成方法。 翅片结构可以形成为使翅片结构的侧壁部分的表面垂直于第一结晶方向。 翅片结构端部的锥形区域可以垂直于第二晶体方向。 可以对翅片结构进行晶体依赖蚀刻。 晶体依赖蚀刻可以相对较快地从第二晶体方向垂直于翅片的部分去除材料，从而形成相对均匀的宽度鳍片结构。
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公开(公告)号：US08236610B2
公开(公告)日：2012-08-07
申请号：US12471656
申请日：2009-05-26
CPC分类号： H01L24/14 , H01L21/6836 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L27/0207 , H01L29/0657 , H01L2224/0401 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/06183 , H01L2224/13009 , H01L2224/13099 , H01L2224/131 , H01L2224/14183 , H01L2224/16 , H01L2224/16105 , H01L2224/16137 , H01L2224/16147 , H01L2224/81205 , H01L2224/81801 , H01L2225/06513 , H01L2225/06524 , H01L2225/06551 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.
摘要翻译： 公开了能够形成半导体芯片连接的系统和方法。 在一个实施例中，半导体芯片包括具有一对相对侧面的多面体形状的主体; 以及沿着在多面体形状的一对相对侧之间延伸的一侧延伸的焊料构件。
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公开(公告)号：US08232620B2
公开(公告)日：2012-07-31
申请号：US12870921
申请日：2010-08-30
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.
摘要翻译： 一个结构。 该结构包括：基底; 衬底中的第一电极; 在所述基板和所述电极的顶部上的介电层; 在所述第一介电层上的第二电介质层，所述第二电介质层包括第二电介质材料; 埋入第一介电层中的熔丝元件，其中熔融元件（i）物理分离，（ii）与二者直接物理接触，（iii）被夹在介电层的第一区域和第二区域之间; 以及在所述熔丝元件的顶部上的第二电极，其中所述第一电极和所述第二电极通过所述熔丝元件彼此电耦合。
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公开(公告)号：US20120146112A1
公开(公告)日：2012-06-14
申请号：US13396291
申请日：2012-02-14
IPC分类号： H01L29/772
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66818
摘要： Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.
摘要翻译： 本发明的实施例提供了Fin场效应晶体管（FinFET）中的相对均匀的宽度鳍片及其形成方法。 翅片结构可以形成为使翅片结构的侧壁部分的表面垂直于第一结晶方向。 翅片结构端部的锥形区域可以垂直于第二晶体方向。 可以对翅片结构进行晶体依赖蚀刻。 晶体依赖蚀刻可以相对较快地从第二晶体方向垂直于翅片的部分去除材料，从而形成相对均匀的宽度鳍片结构。
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公开(公告)号：US08115575B2
公开(公告)日：2012-02-14
申请号：US12191519
申请日：2008-08-14
申请人： Louis Lu-Chen Hsu , Jong-Ru Guo , Ping-Chuan Wang , Zhijian Yang
发明人： Louis Lu-Chen Hsu , Jong-Ru Guo , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H03H11/00
摘要： An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.
摘要翻译： 一种使用现有DRAM，SRAM和逻辑处理集成制造低成本高密度紧凑型有源电感模块的装置和方法。 有源电感器模块的元件由包括nMOS器件，深沟槽电容器和多晶硅或TaN电阻器的三个半导体器件形成。 有源电感模块可以并联和/或串联配置连接，以获得宽范围的电感值。 模块化有源电感器可以有利地存储在ASIC库中，以便于灵活和方便的电路设计。
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公开(公告)号：US07930664B2
公开(公告)日：2011-04-19
申请号：US12885727
申请日：2010-09-20
申请人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
发明人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
IPC分类号： G06F17/50
CPC分类号： H01L23/5252 , H01L21/76898 , H01L24/05 , H01L24/08 , H01L25/0657 , H01L25/50 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/05573 , H01L2224/05611 , H01L2224/08146 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/10253 , H01L2924/3011 , H01L2924/00 , H01L2224/05624 , H01L2924/00014 , H01L2224/05647 , H01L2224/05684
摘要： Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.
摘要翻译： 硅芯片中的硅通孔（TSV）都是可编程的和不可编程的。 可编程TSV可以使用金属/绝缘体/金属结构从开放状态切换到短路状态，并且通过在多层芯片堆叠中的两个相邻芯片上的互补电路进行编程。
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公开(公告)号：US07911263B2
公开(公告)日：2011-03-22
申请号：US12494460
申请日：2009-06-30
CPC分类号： H03K17/0822
摘要： A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal switches the target semiconductor device to an active mode for leakage mitigation, which includes a repair voltage from a repair voltage generator applied to the gate of the target semiconductor device.
摘要翻译： 识别泄漏电流目标单元内的休眠模式目标半导体器件，以减轻漏电流，防止其达到灾难性的失控。 泄漏电流移动监视器单元电连接到泄漏电流目标单元的输出节点，并在两个连续的预定义时间周期内从所选择的目标半导体器件收集泄漏电流，并测量所收集的漏电流之间的差异。 比较器接收并比较当前移位监视器单元和参考电压发生器的输出。 当从泄漏电流移动监视器单元输出的泄漏电压超过参考电压时，比较器将报警信号传播到泄漏电流目标单元，表示泄漏电流即将接近灾难性失控水平的条件。 该警报信号将目标半导体器件切换到用于泄漏减轻的活动模式，其包括施加到目标半导体器件的栅极的修复电压发生器的修复电压。
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69.发明授权公开(公告)号：US07737530B2
公开(公告)日：2010-06-15
申请号：US12130176
申请日：2008-05-30
IPC分类号： H01L29/732
CPC分类号： H01L29/732 , H01L29/66265
摘要： Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure includes a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further includes a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.
摘要翻译： 用于双极结晶体管的半导体器件结构和制造这种半导体器件结构的方法。 半导体器件结构包括具有顶表面和从顶表面延伸到绝缘层的侧壁的半导体本体，包括具有第一导电类型的第一半导体材料的第一区域和包括具有第二导电类型的第二半导体材料的第二区域 导电类型。 第一和第二区域各自延伸穿过半导体本体的顶表面和侧壁。 器件结构还包括限定在第一和第二区域之间并且跨越半导体本体的顶表面和侧壁延伸的结。
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公开(公告)号：US07714452B2
公开(公告)日：2010-05-11
申请号：US11847776
申请日：2007-08-30
申请人： Lawrence A. Clevenger , Mukta Ghate Farooq , Louis Lu-Chen Hsu , William Francis Landers , Donna S. Zupanski-Nielson , Carl John Radens , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Mukta Ghate Farooq , Louis Lu-Chen Hsu , William Francis Landers , Donna S. Zupanski-Nielson , Carl John Radens , Chih-Chao Yang
CPC分类号： H05K3/3436 , H01L23/13 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/49 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/06102 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/49109 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H05K2201/094 , H05K2201/09736 , H05K2201/09845 , Y02P70/613 , H01L2224/29099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.
摘要翻译： 一种电结构和方法，包括电和机械地连接到第二衬底的第一衬底。 第一基板包括第一导电焊盘和第二导电焊盘。 第二基板包括第三导电焊盘，第四导电焊盘和第一导电部件。 第四导电焊盘包括与第一导电构件的高度不同的高度。 导电构件电连接和机械地连接到第四导电垫。 第一焊球将第一导电焊盘连接到第三导电焊盘。 第一焊球包括第一直径。 第二焊球将第二导电焊盘连接到第一导电构件。 第二焊球包括第二直径。 第一直径大于所述第二直径。
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