公开(公告)号：US09806011B2

公开(公告)日：2017-10-31

申请号：US14974726

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1517 ,  H01L2924/15311

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US20170040264A1

公开(公告)日：2017-02-09

申请号：US15297005

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5381 ,  G06F17/5077 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及互连路由配置和相关技术。 在一个实施例中，一种装置包括基板，设置在基板上并具有第一多个迹线的第一布线层和与第一布线层直接相邻设置且具有第二多个迹线的第二布线层，其中第一布线层 第一多个迹线的迹线具有大于第二多个迹线的第二迹线的宽度的宽度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US12159840B2

公开(公告)日：2024-12-03

申请号：US16910023

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Juan Zeng ,  Peipei Wang ,  Ahmad Siddiqui ,  Lakshmipriya Seshan

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/538

Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

公开(公告)号：US12107060B2

公开(公告)日：2024-10-01

申请号：US17025843

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Mohammad Enamul Kabir ,  Han Wui Then ,  Kimin Jun ,  Kevin P. O'Brien ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/05147 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09055 ,  H01L2224/29186 ,  H01L2224/32145

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US12100662B2

公开(公告)日：2024-09-24

申请号：US17127304

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

IPC: H01L23/538 ,  H01L21/50 ,  H01L23/50 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/50 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

公开(公告)号：US20230420377A1

公开(公告)日：2023-12-28

申请号：US17847257

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Cemil Geyik ,  Kemal Aygun ,  Zhiguo Qian ,  Kristof Kuwawi Darmawikarta ,  Zhichao Zhang

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/16

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate comprising a conductive trace in a dielectric material, the conductive trace surrounded by a conductive structure coupled to a ground connection, the package substrate further comprising metallization layers alternating with dielectric layers of the dielectric material; and an integrated circuit (IC) die coupled to a surface of the package substrate, the IC die being coupled to the conductive trace by a conductive pathway. The dielectric layers and the metallization layers are parallel to the surface of the package substrate, the conductive trace comprises a trench via in one of the dielectric layers, and the conductive structure comprises grounded plates extending across a length and width of the package substrate in metallization layers on either side of the dielectric layer.

公开(公告)号：US11456281B2

公开(公告)日：2022-09-27

申请号：US16147742

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Yí Li ,  Zhiguo Qian ,  Prasad Ramanathan ,  Saikumar Jayaraman ,  Kemal Aygun ,  Hector Amador ,  Andrew Collins ,  Jianyong Xie ,  Shigeki Tomishima

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/00

Abstract: Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

公开(公告)号：US20220130763A1

公开(公告)日：2022-04-28

申请号：US17572167

申请日：2022-01-10

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Zhiguo Qian ,  Henning Braunisch ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L25/065

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

公开(公告)号：US20210375746A1

公开(公告)日：2021-12-02

申请号：US16884452

申请日：2020-05-27

Applicant: INTEL CORPORATION

Inventor： Hongxia Feng ,  Jeremy Ecton ,  Aleksandar Aleksov ,  Haobo Chen ,  Xiaoying Guo ,  Brandon C. Marin ,  Zhiguo Qian ,  Daryl Purcell ,  Leonel Arana ,  Matthew Tingey

IPC: H01L23/522 ,  H01L23/66

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

公开(公告)号：US20210057345A1

公开(公告)日：2021-02-25

申请号：US17091657

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.