公开(公告)号：US20220181252A1

公开(公告)日：2022-06-09

申请号：US17110381

申请日：2020-12-03

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  David Wolpert ,  Takashi Ando ,  Praneet Adusumilli ,  Cheng Chi

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

公开(公告)号：US11245020B2

公开(公告)日：2022-02-08

申请号：US16745100

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/786

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US11137418B2

公开(公告)日：2021-10-05

申请号：US16291755

申请日：2019-03-04

Applicant: International Business Machines Corporation

Inventor： Kushagra Sinha ,  Pablo Nieves ,  Reinaldo Vega

IPC: G01R31/00 ,  G01R1/073 ,  G01R31/28 ,  G01R1/04 ,  G01R3/00

Abstract: A test probe assembly for use in testing a semiconductor wafer includes a probe card, a plurality of test probes mounted to the probe card and one or more piezoelectric elements mounted to each test probe. The piezoelectric elements are configured to move respective probe ends of the individual test probes in at least one direction to facilitate realignment of the probe ends for semiconductor wafer testing.

公开(公告)号：US11125780B2

公开(公告)日：2021-09-21

申请号：US16164223

申请日：2018-10-18

Applicant: International Business Machines Corporation

Inventor： Kushagra Sinha ,  Pablo Nieves ,  Reinaldo Vega

IPC: G01R1/07 ,  G01R31/28

Abstract: A test probe assembly for determining the integrity of a test pad of a semiconductor wafer. The test probe assembly includes a probe card, a plurality of test probes mounted to the probe card, a fiber optic lead mounted to each test probe and arranged to direct incident light toward individual test pads of the semiconductor wafer and a plurality of photodetectors arranged about the probe card. Individual photodetectors are configured to receive light reflected off a dielectric coating of the test pad corresponding to a first set of light rays emitted by the test pad and configured to receive light reflected off a metallic base of the test pad corresponding to a second set of light rays emitted by the test pad, and to generate first and second output signals associated with the first and second sets of light rays to create image data of the individual test pads.

公开(公告)号：US20210242402A1

公开(公告)日：2021-08-05

申请号：US17233968

申请日：2021-04-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jianshi Tang ,  Takashi Ando ,  Reinaldo Vega ,  Praneet Adusumilli

IPC: H01L45/00 ,  H01L27/24

Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.

公开(公告)号：US10915811B1

公开(公告)日：2021-02-09

申请号：US16575380

申请日：2019-09-18

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Jianshi Tang ,  Praneet Adusumilli ,  Reinaldo Vega

IPC: G06N3/063 ,  H01L27/24 ,  G06N3/08

Abstract: An electro-chemical random-access memory (ECRAM) cell includes a substrate and a plurality of source-drain pairs positioned on a top surface of the substrate, each source-drain pair comprising a source and a drain. A channel at least partially overlays the substrate and the plurality of source-drain pairs, and a transfer layer at least partially overlays the channel. A gate at least partially overlays the transfer layer, the gate at least partially controlling a channel between each source-drain pair.

公开(公告)号：US10903318B2

公开(公告)日：2021-01-26

申请号：US16775726

申请日：2020-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Reinaldo Vega ,  Jingyun Zhang ,  Miaomiao Wang

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.

公开(公告)号：US20200343448A1

公开(公告)日：2020-10-29

申请号：US16394305

申请日：2019-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Praneet Adusumilli ,  Jianshi Tang ,  Reinaldo Vega

IPC: H01L45/00 ,  H01L27/24

Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.

公开(公告)号：US10770512B1

公开(公告)日：2020-09-08

申请号：US16368065

申请日：2019-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Takashi Ando ,  Hari Mallela ,  Li-Wen Hung

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.

公开(公告)号：US20200279918A1

公开(公告)日：2020-09-03

申请号：US16290611

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Ruqiang Bao ,  Junli Wang ,  Lan Yu ,  Reinaldo Vega ,  Adra Carr

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.