公开(公告)号：US12261146B2

公开(公告)日：2025-03-25

申请号：US18336067

申请日：2023-06-16

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber

IPC: H01L23/00

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

公开(公告)号：US11984392B2

公开(公告)日：2024-05-14

申请号：US17459296

申请日：2021-08-27

Applicant: Infineon Technologies AG

Inventor： Chee Yang Ng ,  Stefan Woetzel ,  Edward Fuergut ,  Thai Kee Gan ,  Chee Hong Lee ,  Jayaganasan Narayanasamy ,  Ralf Otremba

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L23/492 ,  H01L23/538 ,  H01L29/66 ,  H01L23/31

CPC classification number: H01L23/49844 ,  H01L23/3735 ,  H01L23/4924 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/08 ,  H01L24/14 ,  H01L24/16 ,  H01L29/66431 ,  H01L23/3185 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/0556 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/32227 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091

Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

公开(公告)号：US11646258B2

公开(公告)日：2023-05-09

申请号：US16944303

申请日：2020-07-31

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Thomas Basler ,  Reinhold Bayerer ,  Ivan Nikitin

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/56 ,  H01L21/48 ,  H01L23/29

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/293 ,  H01L23/66 ,  H01L2223/6605

Abstract: An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.

公开(公告)号：US20220157686A1

公开(公告)日：2022-05-19

申请号：US17097098

申请日：2020-11-13

Applicant: Infineon Technologies AG

Inventor： Jo Ean Joanna Chye ,  Edward Fuergut ,  Ralf Otremba

IPC: H01L23/367 ,  H01L23/31

Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

公开(公告)号：US10685909B2

公开(公告)日：2020-06-16

申请号：US15816090

申请日：2017-11-17

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Martin Gruber

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/11 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device package includes a lead frame, a first power semiconductor device mounted on a first part of the lead frame and a second power semiconductor device mounted on a second part of the lead frame. The first power semiconductor device is encapsulated by a first mold compound. The second power semiconductor device is encapsulated by a second mold compound. The first mold compound and the second mold compound are substantially separate from each other. The lead frame includes an intermediate part arranged between the first part and the second part. The intermediate part is not covered by the first mold compound or by the second mold compound.

公开(公告)号：US20200013723A1

公开(公告)日：2020-01-09

申请号：US16453222

申请日：2019-06-26

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ravi Keshav Joshi ,  Ralf Siemieniec ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Dethard Peters ,  Roland Rupp ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L29/16 ,  H01L29/45 ,  H01L21/768 ,  H01L23/00

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

公开(公告)号：US10177112B2

公开(公告)日：2019-01-08

申请号：US15422674

申请日：2017-02-02

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Georg Meyer-Berg

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498

Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.

公开(公告)号：US10049962B2

公开(公告)日：2018-08-14

申请号：US15171364

申请日：2016-06-02

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Edward Fuergut ,  Joachim Mahler

IPC: H01L23/13 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065 ,  H01L23/44 ,  H01L25/07 ,  H05K7/20 ,  H05K7/08 ,  H05K7/10 ,  H05K7/02 ,  H01L23/00

Abstract: A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

公开(公告)号：US09984928B2

公开(公告)日：2018-05-29

申请号：US15378669

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Peter Kanschat

IPC: H01L21/44 ,  H01L21/78 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

公开(公告)号：US09966277B2

公开(公告)日：2018-05-08

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L27/02 ,  H01L23/31 ,  H01L29/861

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.