公开(公告)号：US20110111559A1

公开(公告)日：2011-05-12

申请号：US13006227

申请日：2011-01-13

申请人： James G. Mitchell ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

发明人： James G. Mitchell ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

IPC分类号： H01L21/50

CPC分类号： H01L25/0652 ,  H01L23/10 ,  H01L23/48 ,  H01L24/02 ,  H01L24/16 ,  H01L24/72 ,  H01L24/81 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/73251 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/95136 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/16 ,  H01L2224/72

摘要： Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.

摘要翻译： 描述了多芯片模块（MCM）的实施例。 该MCM包括第一半导体管芯和第二半导体管芯，其中可以是第一半导体管芯或第二半导体管芯的给定半导体管芯包括靠近给定半导体管芯的表面的接近连接器。 此外，给定的半导体管芯被配置为通过一个或多个接近连接器的接近通信与另一个半导体管芯通信信号。 此外，MCM包括对准板和联接到对准板的顶板。 该对准板包括被配置为容纳第一半导体管芯的第一负特征构件和被配置为容纳第二半导体管芯的第二负特征，并且顶板包括正特征。 注意，正特征耦合到第一半导体管芯，并且正特征有利于第一半导体管芯的机械定位。

公开(公告)号：US07893531B2

公开(公告)日：2011-02-22

申请号：US11864408

申请日：2007-09-28

申请人： James G. Mitchell ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

发明人： James G. Mitchell ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

IPC分类号： H01L23/34

CPC分类号： H01L25/0652 ,  H01L23/10 ,  H01L23/48 ,  H01L24/02 ,  H01L24/16 ,  H01L24/72 ,  H01L24/81 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/73251 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/95136 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/16 ,  H01L2224/72

摘要： Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.

公开(公告)号：US07888175B2

公开(公告)日：2011-02-15

申请号：US12502156

申请日：2009-07-13

申请人： Ashok V. Krishnamoorthy ,  John E. Cunningham

发明人： Ashok V. Krishnamoorthy ,  John E. Cunningham

IPC分类号： H01L21/60 ,  H01L29/40

CPC分类号： H01L23/48 ,  G02B6/12007 ,  G02B6/29341 ,  G02B6/43 ,  H01L24/10 ,  H01L24/13 ,  H01L24/72 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/2919 ,  H01L2224/81138 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2224/83141 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2225/06527 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10157 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： The described embodiments provide a system that facilitates inter-chip alignment for proximity communication and power delivery. The system includes a first integrated circuit chip and a second integrated circuit chip, both of which whose surfaces have corresponding etch pit wells configured to align with each other. A shaped structure is placed in an etch pit well of the first integrated circuit chip such that when the corresponding etch pit well of the second integrated circuit chip is substantially aligned with the etch pit well of the first integrated circuit chip, the shaped structure mates with both the etch pit well of the first integrated circuit chip and with the corresponding etch pit well of the second integrated circuit chip, thereby aligning the first integrated circuit chip with the second integrated circuit chip. In some embodiments the etch pit wells include conductive structures for routing power through a conductive shaped structure.

摘要翻译： 所描述的实施例提供了一种促进接近通信和功率传递的芯片间对准的系统。 该系统包括第一集成电路芯片和第二集成电路芯片，它们的两个表面具有被配置为彼此对准的相应蚀刻凹坑。 成形结构放置在第一集成电路芯片的蚀刻凹坑中，使得当第二集成电路芯片的相应蚀刻凹坑与第一集成电路芯片的蚀刻凹坑基本对准时，成形结构与 第一集成电路芯片的蚀刻凹坑以及第二集成电路芯片的相应蚀刻凹坑两者，从而使第一集成电路芯片与第二集成电路芯片对准。 在一些实施例中，蚀刻坑井包括用于通过导电成形结构路由功率的导电结构。

公开(公告)号：US07646984B1

公开(公告)日：2010-01-12

申请号：US11728915

申请日：2007-03-26

申请人： Ronald Ho ,  John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Robert J. Drost

发明人： Ronald Ho ,  John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Robert J. Drost

IPC分类号： H04B10/12

CPC分类号： G06F1/105

摘要： Embodiments of an integrated circuit are described. This integrated circuit includes: a clock-generator circuit configured to provide a clock signal; an optical clock path coupled to the clock-generator circuit; and a latch coupled to the optical clock path. This optical clock path is configured to distribute an optical signal corresponding to the clock signal. Furthermore, the optical clock path is configured to optically set a skew value for the optical signal, and is configured to selectively gate distribution of the optical signal to the latch based on activity of the latch. Note that the selective gating is performed optically.

摘要翻译： 描述集成电路的实施例。 该集成电路包括：时钟发生器电路，被配置为提供时钟信号; 耦合到时钟发生器电路的光时钟通路; 以及耦合到光时钟路径的锁存器。 该光时钟路径被配置为分配对应于时钟信号的光信号。 此外，光时钟路径被配置为光学地设置光信号的偏斜值，并且被配置为基于锁存器的活动来选择性地将光信号分配到锁存器。 注意，选择性门控是光学执行的。

公开(公告)号：US20090280601A1

公开(公告)日：2009-11-12

申请号：US12502156

申请日：2009-07-13

申请人： Ashok V. Krishnamoorthy ,  John E. Cunningham

发明人： Ashok V. Krishnamoorthy ,  John E. Cunningham

IPC分类号： H01L21/50

CPC分类号： H01L23/48 ,  G02B6/12007 ,  G02B6/29341 ,  G02B6/43 ,  H01L24/10 ,  H01L24/13 ,  H01L24/72 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/2919 ,  H01L2224/81138 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2224/83141 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2225/06527 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10157 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： The described embodiments provide a system that facilitates inter-chip alignment for proximity communication and power delivery. The system includes a first integrated circuit chip and a second integrated circuit chip, both of which whose surfaces have corresponding etch pit wells configured to align with each other. A shaped structure is placed in an etch pit well of the first integrated circuit chip such that when the corresponding etch pit well of the second integrated circuit chip is substantially aligned with the etch pit well of the first integrated circuit chip, the shaped structure mates with both the etch pit well of the first integrated circuit chip and with the corresponding etch pit well of the second integrated circuit chip, thereby aligning the first integrated circuit chip with the second integrated circuit chip. In some embodiments the etch pit wells include conductive structures for routing power through a conductive shaped structure.

摘要翻译： 所描述的实施例提供了一种促进接近通信和功率传递的芯片间对准的系统。 该系统包括第一集成电路芯片和第二集成电路芯片，它们的两个表面具有被配置为彼此对准的相应蚀刻凹坑。 成形结构放置在第一集成电路芯片的蚀刻凹坑中，使得当第二集成电路芯片的相应蚀刻凹坑与第一集成电路芯片的蚀刻凹坑基本对准时，成形结构与 第一集成电路芯片的蚀刻凹坑以及第二集成电路芯片的相应蚀刻凹坑两者，从而使第一集成电路芯片与第二集成电路芯片对准。 在一些实施例中，蚀刻坑井包括用于通过导电成形结构路由功率的导电结构。

公开(公告)号：US20090179334A1

公开(公告)日：2009-07-16

申请号：US12391137

申请日：2009-02-23

申请人： Ashok V. Krishnamoorthy ,  John E. Cunningham

发明人： Ashok V. Krishnamoorthy ,  John E. Cunningham

IPC分类号： H01L23/482

CPC分类号： H01L23/48 ,  H01L25/0652 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip. Then, an identified portion of the active face of the bridge chip is thinned via etching and is removed by planarizing the back face of the bridge chip, thereby creating an opening in the bridge chip that exposes a portion of the active face of the base chip.

摘要翻译： 本发明的一个实施例提供一种用于促进半导体芯片之间的邻近通信的系统。 该系统包括一个基片和一个桥芯片，每个芯片包括有源电路和信号焊盘所在的有源面以及与有源面相对的背面。 桥芯片的主动面接合到基片的有源面。 然后，通过蚀刻使桥接芯片的有源面的识别部分变薄，并且通过平坦化桥芯片的背面去除，从而在桥芯片中形成露出基片的有源面的一部分的开口 。

公开(公告)号：US07356213B1

公开(公告)日：2008-04-08

申请号：US11728843

申请日：2007-03-26

申请人： John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Ronald Ho ,  Robert J. Drost

发明人： John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Ronald Ho ,  Robert J. Drost

IPC分类号： G02B6/12

CPC分类号： H01L23/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of a switch are described. This switch includes input ports configured to receive signals (which include data) and output ports configured to output the signals. In addition, the switch includes switching elements and a flow-control mechanism, which is configured to provide flow-control information associated with the data to the switching elements via an optical control path. These switching elements are configured to selectively couple the input ports to the output ports based on the flow-control information. Furthermore, a given switching element in the switching elements is coupled to a given input port and a given output port via electrical signal paths that are configured to use proximity communication to communicate the data.

摘要翻译： 描述开关的实施例。 该开关包括被配置为接收被配置为输出信号的信号（其包括数据）和输出端口的输入端口。 此外，开关包括开关元件和流量控制机构，其被配置为经由光学控制路径向开关元件提供与数据相关联的流量控制信息。 这些开关元件被配置为基于流量控制信息选择性地将输入端口耦合到输出端口。 此外，开关元件中的给定开关元件通过经配置以使用接近通信来传送数据的电信号路径耦合到给定输入端口和给定输出端口。

公开(公告)号：US20120326322A1

公开(公告)日：2012-12-27

申请号：US13165599

申请日：2011-06-21

申请人： Ashok V. Krishnamoorthy ,  Craig A. Stephen ,  John E. Cunningham ,  James G. Mitchell

发明人： Ashok V. Krishnamoorthy ,  Craig A. Stephen ,  John E. Cunningham ,  James G. Mitchell

IPC分类号： H01L23/48 ,  B32B3/00

CPC分类号： H01L24/13 ,  H01L23/48 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/81097 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81815 ,  H01L2224/81855 ,  Y10T428/24479 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01082 ,  H01L2924/0105

摘要： A chip package includes a substrate having a positive feature, which is defined on a surface of the substrate and which protrudes above a region on the surface proximate to the positive feature. Furthermore, the chip package includes a mechanical reinforcement mechanism defined on the substrate proximate to the positive feature that increases a lateral shear strength of the positive feature relative to the substrate. In this way, the chip package may facilitate increased reliability of a multi-chip module (MCM) that includes the chip package.

摘要翻译： 芯片封装包括具有正特征的衬底，其被限定在衬底的表面上并且突出在接近正特征的表面上的区域上方。 此外，芯片封装包括限定在靠近正特征的基板上的机械加强机构，其增加正特征相对于基板的横向剪切强度。 以这种方式，芯片封装可以促进包括芯片封装的多芯片模块（MCM）的增加的可靠性。

公开(公告)号：US20120220056A1

公开(公告)日：2012-08-30

申请号：US13467671

申请日：2012-05-09

申请人： Jing Shi ,  Hiren D. Thacker ,  Ashok V. Krishnamoorthy ,  John E. Cunningham

发明人： Jing Shi ,  Hiren D. Thacker ,  Ashok V. Krishnamoorthy ,  John E. Cunningham

IPC分类号： H01L21/02

CPC分类号： H01L23/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates.

摘要翻译： 描述了多芯片模块（MCM）。 该MCM包括至少两个基板，其通过在基板的相对表面上的正和负特征可重新机械耦合。 这些正面和负面的特征相互交织在一起。 特别地，正特征可以与给定的一对负特征匹配，其包括每个基底上的负特征。 此外，给定对中的负特征中的至少一个可以包括硬磁材料，并且给定对中的正特征和另一个负特征可以包括软磁材料，其提供到硬磁体的通量回流路径 材料。 以这种方式，硬磁材料可以促进基板的可重新机械耦合。

公开(公告)号：US20110302465A1

公开(公告)日：2011-12-08

申请号：US13212900

申请日：2011-08-18

申请人： Ronald Ho ,  Ashok V. Krishnamoorthy ,  John E. Cunningham ,  Robert J. Drost

发明人： Ronald Ho ,  Ashok V. Krishnamoorthy ,  John E. Cunningham ,  Robert J. Drost

IPC分类号： G06F11/07

CPC分类号： H04B5/0075 ,  H01L25/065 ,  H01L2924/0002 ,  H04B17/318 ,  H04L1/0009 ,  Y10T29/49133 ,  H01L2924/00

摘要： In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels.

摘要翻译： 在接近通信系统中，一个芯片上的发射元件与与第一芯片并置的第二芯片上的接收元件对齐。 然而，如果元件是静态的或动态的，则芯片之间的耦合会降低。 可以通过可控地降低系统的性能来补偿未对准。 例如，可以增加发射信号强度。 可以增加用于偏置每个位的位周期或时间段，从而降低带宽。 诸如电容器的多个耦合元件可以组合在一起，从而减少通道数量。 可以通过减少每个符号的比特数来增加诸如图像的符号的粒度。 诸如电容器的多个耦合元件可以组合在一起，从而减少通道数量。