公开(公告)号：US08722466B2

公开(公告)日：2014-05-13

申请号：US12722528

申请日：2010-03-12

申请人： Jun Lu ,  Kai Liu ,  Yan Xun Xue

发明人： Jun Lu ,  Kai Liu ,  Yan Xun Xue

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/565 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L25/07 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

摘要翻译： 具有用于内部连接的连接板的半导体封装包括：多个芯片，每个芯片在顶表面上具有多个接触区域; 一个或多个连接板具有多个电隔离的连接板部分，每个连接板部分连接半导体芯片的接触区域。 制造半导体封装的方法包括将一个或多个连接板连接到多个半导体芯片的步骤，施加模制材料以封装芯片和连接板，将连接板的多个连接板部分分开浅 切割或磨削。

公开(公告)号：US20120193695A1

公开(公告)日：2012-08-02

申请号：US13442757

申请日：2012-04-09

申请人： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

发明人： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC分类号： H01L27/06

CPC分类号： H01L23/49575 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/84

摘要： A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.

摘要翻译： 用于功率转换器应用的半导体封装包括低边MOSFET芯片和高边MOSFET芯片。 半导体封装可以进一步包围电容器，而电容器可以是分立元件或芯片级与低边MOSFET的集成元件。 半导体封装还可以包括PIC芯片，以在半导体芯片组件封装级别上提供完整的功率转换器。

公开(公告)号：US08178954B2

公开(公告)日：2012-05-15

申请号：US12693446

申请日：2010-01-26

申请人： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

发明人： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/02

CPC分类号： H01L23/49575 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/84

摘要： A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.

摘要翻译： 用于功率转换器应用的半导体封装包括低边MOSFET芯片和高边MOSFET芯片。 半导体封装可以进一步包围电容器，而电容器可以是分立元件或芯片级与低边MOSFET的集成元件。 半导体封装还可以包括PIC芯片，以在半导体芯片组件封装级别上提供完整的功率转换器。

公开(公告)号：US08076183B2

公开(公告)日：2011-12-13

申请号：US12606290

申请日：2009-10-27

申请人： Yan Xun Xue ,  Jun Lu ,  Le Shi ,  Liang Zhao

发明人： Yan Xun Xue ,  Jun Lu ,  Le Shi ,  Liang Zhao

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L24/73 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.

摘要翻译： 公开了一种将引线框封装内的互连板连接到半导体管芯的方法。 基座引线框架设置有用于附接半导体管芯的管芯焊盘。 提供互连板，用于附接到基底引线框架和半导体管芯。 将基准注册功能添加到基准引线框架和板对准特征到互连板上，其中配准特征被设计成彼此匹配，使得在互连板到基底引线框架的接近时，两个配准特征将相互接合并引导彼此引起伴随 互连板与基座引线框架的自对准连接。 接下来，使互连板靠近基底引线框架以将板对准特征接合并锁定到基准对准特征，从而完成互连板连接到半导体管芯并形成引线框封装。

公开(公告)号：US08519525B2

公开(公告)日：2013-08-27

申请号：US12846034

申请日：2010-07-29

申请人： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

发明人： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC分类号： H01L23/495

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40248 ,  H01L2224/40249 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.

摘要翻译： 半导体封装包括引线框架，还包括芯片载体和与芯片载体相邻的多个引脚。 从芯片载体的上表面开放的多个槽将芯片载体部分地分成多个芯片安装区域。 去除凹槽的底部以完全隔离每个芯片安装区域，其中移除的凹槽的底部的宽度小于凹槽的宽度。 在一个实施例中，凹槽位于芯片载体和引脚之间，其中凹槽的底部被移除以将引脚与芯片载体隔离开，其中移除的凹槽的底部的宽度小于凹槽的宽度 。

公开(公告)号：US08482048B2

公开(公告)日：2013-07-09

申请号：US12947107

申请日：2010-11-16

申请人： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

发明人： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L23/5223 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.

摘要翻译： 旁路电容直接集成在MOSFET芯片的顶部。 电容器包括多层导电材料和电介质材料，它们通过介电层连接不同导电层的连接通孔彼此顶部。 集成旁路电容器的方法包括沉积介电层的重复步骤，形成通过电介质层的连接通孔，沉积导电层和图案化导电层。

公开(公告)号：US08283212B2

公开(公告)日：2012-10-09

申请号：US12980309

申请日：2010-12-28

申请人： Yan Xun Xue ,  Jun Lu ,  Anup Bhalla

发明人： Yan Xun Xue ,  Jun Lu ,  Anup Bhalla

IPC分类号： H01L21/00 ,  H01L21/60

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for making a wire bond package comprising the step of providing a lead frame array comprising a plurality of lead frame units therein, each lead frame unit comprises a first die pad and a second die pad each having a plurality of tie bars connected to the lead frame array, a plurality of reinforced bars interconnecting the first and second die pads; the reinforced bars are removed after molding compound encapsulation.

摘要翻译： 一种用于制造引线接合封装的方法，包括提供包括多个引线框架单元的引线框架阵列的步骤，每个引线框架单元包括第一管芯焊盘和第二管芯焊盘，每个引线框架单元具有连接到 引线框架阵列，互连第一和第二管芯焊盘的多个加强杆; 在模塑复合材料封装之后去除增强棒。

公开(公告)号：US20110062506A1

公开(公告)日：2011-03-17

申请号：US12947107

申请日：2010-11-16

申请人： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

发明人： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L27/06

CPC分类号： H01L23/5223 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.

摘要翻译： 旁路电容直接集成在MOSFET芯片的顶部。 电容器包括多层导电材料和电介质材料，它们通过介电层连接不同导电层的连接通孔彼此顶部。 集成旁路电容器的方法包括沉积介电层的重复步骤，形成通过电介质层的连接通孔，沉积导电层和图案化导电层。

公开(公告)号：US20110059593A1

公开(公告)日：2011-03-10

申请号：US12947717

申请日：2010-11-16

申请人： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

发明人： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L21/02

CPC分类号： H01L23/5223 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0688 ,  H01L28/88 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.

摘要翻译： 旁路电容直接集成在MOSFET芯片的顶部。 电容器包括多层导电材料和电介质材料，它们通过介电层连接不同导电层的连接通孔彼此顶部。 集成旁路电容器的方法包括沉积介电层的重复步骤，形成通过电介质层的连接通孔，沉积导电层和图案化导电层。

公开(公告)号：US08513784B2

公开(公告)日：2013-08-20

申请号：US12726892

申请日：2010-03-18

申请人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

发明人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73263 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.

摘要翻译： 本发明的特征在于具有第一，第二，第三和第四导电结构的引线框架封装，其中设置在其间的一对半导体管芯限定堆叠结构。 第一和第二结构与第一结构隔开并与第一结构重叠。 半导体管芯设置在第一和第二结构之间。 半导体管芯具有电连接到第一和第二结构的触点。 第三结构的一部分位于具有第二结构的一部分的共同平面中。 第三结构耦合到半导体管芯。 附加的半导体管芯附接到第一和第二结构中的一个。 第四结构与附加的半导体管芯电接触。 设置模塑料以封装所述包装的一部分，其中模制化合物的一部分设置在体积中。