公开(公告)号：US20060154425A1

公开(公告)日：2006-07-13

申请号：US11032439

申请日：2005-01-10

申请人： Ming-Ho Yang ,  Karen Mai ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Ming-Ho Yang ,  Karen Mai ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28061 ,  H01L21/28194 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device and method for fabricating the same. The semiconductor device comprises a substrate with a gate stack thereon, wherein the gate stack comprises a high-k dielectric layer and a conductive layer sequentially overlying a portion of the substrate. An oxidation-proof layer overlies sidewalls of the gate stack. A pair of insulating spacers oppositely overlies sidewalls of the gate stack and the oxidation-proof layers thereon and a pair of source/drain regions is oppositely formed in the substrate adjacent to the gate stack, wherein the oxidation-proof layer suppresses oxidation encroachment between the gate stack and the substrate.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件包括其上具有栅极堆叠的衬底，其中栅极堆叠包括高k电介质层和顺序地覆盖衬底的一部分的导电层。 防氧化层覆盖在栅叠层的侧壁上。 一对绝缘隔片相对地覆盖在栅堆叠的侧壁和其上的防氧化层上，并且一对源极/漏极区域相邻地形成在与栅极叠层相邻的衬底中，其中防氧化层抑制了栅极叠层之间的氧化侵蚀 栅极堆叠和衬底。

公开(公告)号：US20050196927A1

公开(公告)日：2005-09-08

申请号：US11119951

申请日：2005-05-02

申请人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  Y10S257/90

摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

公开(公告)号：US20050093084A1

公开(公告)日：2005-05-05

申请号：US10872095

申请日：2004-06-18

申请人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

发明人： Chih-Hao Wang ,  Shang-Chih Chen ,  Yen-Ping Wang ,  Hsien-Kuang Chiu ,  Liang-Gi Yao ,  Chenming Hu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/1054 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。 栅极电介质突出超过栅电极。 在栅极的任一侧形成具有浅延伸的深源极和漏极。 深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。 延伸部位于与栅极电介质接触的栅极下方。 选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。 描述制造MOSFET的方法。

公开(公告)号：US20050074978A1

公开(公告)日：2005-04-07

申请号：US10677158

申请日：2003-10-01

申请人： Ming-Fang Wang ,  Tuo-Hung Hou ,  Kai-Lin Mai ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Ming-Fang Wang ,  Tuo-Hung Hou ,  Kai-Lin Mai ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/28185 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.

摘要翻译： 一种用于处理包括高K栅极电介质堆叠的栅极结构以改善电性能特性的方法，包括在硅衬底上提供包括二元氧化物的栅极介电层堆叠; 在所述栅极介电层堆叠上形成多晶硅层; 光刻图案化和蚀刻以形成栅极结构; 以及进行包括选自H 2，N 2，O 2和NH 3的等离子体源气体的栅极结构的至少一个等离子体处理。

公开(公告)号：US20050056900A1

公开(公告)日：2005-03-17

申请号：US10662845

申请日：2003-09-15

申请人： Ming-Fang Wang ,  Chia-Lin Chen ,  Chih-Wei Yang ,  Chi-Chun Chen ,  Tuo-Hung Hou ,  Yeou-Ming Lin ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Ming-Fang Wang ,  Chia-Lin Chen ,  Chih-Wei Yang ,  Chi-Chun Chen ,  Tuo-Hung Hou ,  Yeou-Ming Lin ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3141 ,  H01L29/513

摘要： A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

摘要翻译： 一种用于形成在栅极结构形成工艺中具有改进的电性能的改进的栅极堆叠结构的方法用于形成高介电常数栅极结构的方法，包括提供包括暴露表面部分的硅衬底; 在暴露的表面部分上形成具有小于约10埃的厚度的界面层; 在介电常数大于约10的界面层上形成高介电常数金属氧化物层; 在高介电常数金属氧化物层上形成阻挡层; 在阻挡层上形成电极层; 并且根据蚀刻图案通过电极层，阻挡层，高介电常数材料层和界面层的厚度进行蚀刻，以形成高介电常数栅极结构。

公开(公告)号：US06706581B1

公开(公告)日：2004-03-16

申请号：US10282387

申请日：2002-10-29

申请人： Tou-Hung Hou ,  Ming-Fang Wang ,  Chi-Chun Chen ,  Chih-Wei Yang ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Tou-Hung Hou ,  Ming-Fang Wang ,  Chi-Chun Chen ,  Chih-Wei Yang ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L218238

CPC分类号： H01L21/823456 ,  H01L21/823462

摘要： A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT

摘要翻译： 描述了可扩展以满足对于50nm和70nm技术节点的要求的形成双栅极电介质层的方法。 衬底具有分离器件区域的STI区域。 界面层和高k电介质层依次沉积在衬底上。 在一个器件区域上去除两个层，并且在暴露的器件区域上生长具有EOT <10nm的超薄氮氧化硅层。 在SiON介电层的生长期间，高k电介质层退火。 高k电介质层由金属氧化物或其硅酸盐或铝酸盐形成，并且能够以具有抑制的漏电流的EOT <1.8nm制造低功率器件。 当形成多个栅极时，该方法与双重或三重氧化物厚度工艺兼容。

公开(公告)号：US06656764B1

公开(公告)日：2003-12-02

申请号：US10146287

申请日：2002-05-15

申请人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L2100

CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  Y10S257/90

摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

摘要翻译： 已经开发了CMOS器件结构，以及制造具有由高k金属氧化物层构成的栅极绝缘体层的CMOS器件的方法。 在沉积高k金属氧化物层之前，该工艺特征是形成凹陷的，重掺杂的源极/漏极区域以及垂直的多晶硅LDD间隔物。 先前用作凹陷区域的掩模的氮化硅形状的去除，其又用于重掺杂源极/漏极区域的适应，提供了由高k金属氧化物层占据的空间。 通过延迟沉积金属氧化物层，在高温下进行保存，通过垂直多晶硅间隔物对接的高k栅极绝缘体层的完整性，并覆盖由半导体衬底的非凹陷部分提供的沟道区域 退火如重掺杂源极/漏极区的激活退火，以及用于金属硅化物形成的退火。

公开(公告)号：US5962344A

公开(公告)日：1999-10-05

申请号：US999229

申请日：1997-12-29

申请人： Yeur-Luen Tu ,  Shiang-Peng Cheng ,  Kwong-Jr Tsai ,  Liang-Gi Yao

发明人： Yeur-Luen Tu ,  Shiang-Peng Cheng ,  Kwong-Jr Tsai ,  Liang-Gi Yao

IPC分类号： H01L21/318 ,  H01L21/441

CPC分类号： H01L21/3185

摘要： A plasma treatment method used to form improved PECVD silicon nitride film passivation layers over metal interconnections on ULSI circuits is achieved. The process is carried out in a single PECVD reactor. After depositing a thin silicon oxide stress-release layer over the metal lines, a plasma-enhanced CVD silicon nitride layer is deposited, and subsequently a plasma treatment step is carried out on the silicon nitride layer. The use of a sufficiently thin silicon nitride layer eliminates photoresist trapping at the next photoresist process step that would otherwise be trapped in the voids (keyholes) that typically form in the silicon nitride passivation layer between the closely spaced metal lines, and can cause corrosion of the metal. The plasma treatment in He, Ar, or a mixture of the two, is then used to densify the silicon nitride layer and to substantially reduce pinholes that would otherwise cause interlevel metal shorts.

摘要翻译： 实现了用于在ULSI电路上的金属互连上形成改进的PECVD氮化硅膜钝化层的等离子体处理方法。 该过程在单个PECVD反应器中进行。 在金属线上沉积薄氧化硅应力释放层之后，沉积等离子体增强的CVD氮化硅层，随后在氮化硅层上进行等离子体处理步骤。 使用足够薄的氮化硅层在下一个光刻胶工艺步骤消除光致抗蚀剂捕获，否则将被捕获在通常在紧密间隔的金属线之间的氮化硅钝化层中形成的空隙（键槽）中，并且可能导致腐蚀 金属。 然后，使用He，Ar中的等离子体处理或两者的混合物来使氮化硅层致密化并且基本上减少否则将引起层间金属短路的针孔。

公开(公告)号：US08470659B2

公开(公告)日：2013-06-25

申请号：US13595599

申请日：2012-08-27

申请人： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

发明人： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC分类号： H01L21/8249

CPC分类号： H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

摘要： This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

摘要翻译： 该描述涉及包括在半导体衬底上形成界面层的方法。 该方法还包括蚀刻回界面层。 该方法还包括在界面层上进行紫外线（UV）固化过程。 UV固化方法包括将每分钟10标准立方厘米（sccm）的气体流速提供到5标准升/分钟（slm），其中气体包括惰性气体，并且在小于或等于的温度下加热界面层 至700℃。该方法还包括在界面层上沉积高k介电材料。

公开(公告)号：US08294201B2

公开(公告)日：2012-10-23

申请号：US13209493

申请日：2011-08-15

申请人： Chen-Hua Yu ,  Liang-Gi Yao

发明人： Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L29/792

CPC分类号： H01L29/517 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.

摘要翻译： 为高k栅极电介质和栅电极提供了一种器件和形成方法。 形成高k电介质材料，并且在高k电介质材料上形成富硅膜。 然后通过氧化或氮化处理富硅膜，以减少由高k材料与随后的栅极导体的结合以及由高k材料与后续栅极导体之间​​的缺乏导致的费米能级钉扎 -k介质材料和栅极导体。 然后通过受控的工艺在膜上形成导电材料以产生栅极导体。