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    MEMORY DEVICE INCLUDING IN-TIER DRIVER CIRCUIT
    62.
    发明申请
    MEMORY DEVICE INCLUDING IN-TIER DRIVER CIRCUIT 有权

    公开(公告)号：US20240420766A1

    公开(公告)日：2024-12-19

    申请号：US18819528

    申请日：2024-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Akira Goda

    IPC: G11C16/08 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.

    BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY
    63.
    发明申请
    BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY 有权

    公开(公告)号：US20240393980A1

    公开(公告)日：2024-11-28

    申请号：US18792881

    申请日：2024-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda ,  Lakshmi Kalpana Vakati ,  Vivek Shivhare ,  Dave Scott Ebsen ,  Sanjay Subbarao

    IPC: G06F3/06

    Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

    TECHNIQUES FOR MANAGING A VOLTAGE RECOVERY OPERATION
    64.
    发明申请
    TECHNIQUES FOR MANAGING A VOLTAGE RECOVERY OPERATION 有权

    公开(公告)号：US20240371452A1

    公开(公告)日：2024-11-07

    申请号：US18648110

    申请日：2024-04-26

    Applicant: Micron Technology, Inc.

    Inventor： Pitamber Shukla, ,  Robert Winston Mason ,  Huai-Yuan Tseng ,  Akira Goda ,  Kishore Kumar Muchherla

    IPC: G11C16/34 ,  G11C16/20

    Abstract: Methods, systems, and devices for techniques for managing a voltage recovery operation are described. In some cases, as part of performing a write command to store data to a set of memory cells, the memory system may store an indication of the initial time at which the write operation occurred, the temperature of the set of memory cells at the initial time, or both. The memory system may subsequently manage an accumulated value based on a duration from the initial time and the temperature of the set of memory cells during the duration. If the accumulated value exceeds an accumulation threshold, the memory system may identify an indication of degradation of the set of memory cells. If the indication exceeds a degradation threshold, the memory system may perform a voltage recovery operation to modify voltages of the set of memory cells.

    BOOST-BY-DECK DURING A PROGRAM OPERATION ON A MEMORY DEVICE
    66.
    发明公开
    BOOST-BY-DECK DURING A PROGRAM OPERATION ON A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240339163A1

    公开(公告)日：2024-10-10

    申请号：US18604411

    申请日：2024-03-13

    Applicant: Micron Technology, Inc.

    Inventor： Leo Raimondo ,  Violante Moschiano ,  Shyam Sunder Raghunathan ,  Akira Goda

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10

    Abstract: Control logic in a memory device initiates a program operation on a memory array comprising a top deck and bottom deck. During a seeding phase of the program operation, the control logic causes a first positive voltage to be applied to a first plurality of wordlines of the memory array, wherein the first plurality of wordlines is associated with memory cells in the bottom deck of the memory array that are in a programmed state, and causes a ground voltage to be applied to a second plurality of wordlines of the memory array, wherein the second plurality of wordlines is associated with memory cells in the top deck of the memory array. At an end of the seeding phase of the program operation, the control logic electrically separates the top deck from the bottom deck and causes a program voltage to be applied to a selected wordline of the memory array during an inhibit phase of the program operation, wherein the selected wordline is associated with respective memory cells in the top deck of the memory array.

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