Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same
    62.
    发明授权
    Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same 有权
    具有隔离元件以减轻边缘效应的非平面微电子器件及其制造方法

    公开(公告)号:US07402856B2

    公开(公告)日:2008-07-22

    申请号:US11299102

    申请日:2005-12-09

    IPC分类号: H01L29/94

    CPC分类号: H01L29/7851 H01L29/66795

    摘要: A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.

    摘要翻译: 非平面微电子器件,制造器件的方法以及包括该器件的系统。 所述非平面微电子器件包括:衬底主体,其包括衬底基座和鳍片,所述鳍片限定其顶部区域处的器件部分; 栅极电介质层,其在所述鳍片的两个横向相对的侧壁上以预定高度延伸,所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层,并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极,并进一步在栅介质层上延伸; 隔离元件,其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限,所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

    Method of patterning a film
    64.
    发明授权
    Method of patterning a film 有权
    图案化方法

    公开(公告)号:US07579280B2

    公开(公告)日:2009-08-25

    申请号:US10859328

    申请日:2004-06-01

    IPC分类号: H01L21/311

    摘要: A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of laterally opposite sidewalls. Next, the mask is removed from above the patterned film. After removing the mask from the patterned film, the protective layer is removed from the sidewalls.

    摘要翻译: 图案化薄膜的方法。 该方法包括在待图案化的膜上形成掩模。 然后将膜与掩模对准地蚀刻以形成具有一对横向相对的侧壁的图案化膜。 在一对横向相对的侧壁上形成保护层。 接下来,从图案化膜的上方去除掩模。 在从图案化的膜去除掩模之后,从侧壁去除保护层。

    Method of fabricating a multi-cornered film
    65.
    发明授权
    Method of fabricating a multi-cornered film 有权
    制造多角膜的方法

    公开(公告)号:US07396711B2

    公开(公告)日:2008-07-08

    申请号:US11320437

    申请日:2005-12-27

    摘要: Embodiments of the present invention describe a method of forming a multi-cornered film. According to the embodiments of the present invention, a photoresist mask is formed on a hard mask film formed on a film. The hard mask film is then patterned in alignment with the photoresist mask to produce a hard mask. The width of the photoresist mask is then reduced to form a reduced width photoresist mask. A first portion of the film is then etched in alignment with the hard mask. The hard mask is then etched in alignment with the reduced width photoresist mask to form a reduced width hard mask. A second portion of the film is then etched in alignment with the reduced width hard mask.

    摘要翻译: 本发明的实施例描述了形成多角膜的方法。 根据本发明的实施例,在形成在膜上的硬掩模膜上形成光致抗蚀剂掩模。 然后将硬掩模膜与光致抗蚀剂掩模对准地图案化以产生硬掩模。 然后将光致抗蚀剂掩模的宽度减小以形成减小宽度的光致抗蚀剂掩模。 然后将膜的第一部分与硬掩模对准地蚀刻。 然后将硬掩模与减小宽度的光刻胶掩模对准地蚀刻以形成减小宽度的硬掩模。 然后将膜的第二部分与减小宽度的硬掩模对准地蚀刻。

    Spacer patterned augmentation of tri-gate transistor gate length
    67.
    发明申请
    Spacer patterned augmentation of tri-gate transistor gate length 有权
    三栅极晶体管栅极长度的间隔图案化扩充

    公开(公告)号:US20090168498A1

    公开(公告)日:2009-07-02

    申请号:US12006063

    申请日:2007-12-28

    IPC分类号: G11C11/40 H01L21/283

    CPC分类号: H01L27/1104 H01L27/0207

    摘要: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.

    摘要翻译: 通常,一方面,一种方法包括形成具有N-扩散和P-扩散区域的半导体衬底。 在半导体衬底上形成栅叠层。 栅电极硬掩模形成在栅叠层上。 栅极电极硬掩模用隔离材料增加在通过栅极晶体管周围。 使用增强的栅极电极硬掩模蚀刻栅极堆叠以形成栅电极。 通过栅极周围的栅电极具有比其它栅电极更大的长度。

    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
    70.
    发明授权
    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication 有权
    非平面半导体器件部分或完全缠绕在栅极电极和制造方法

    公开(公告)号:US07456476B2

    公开(公告)日:2008-11-25

    申请号:US10607769

    申请日:2003-06-27

    IPC分类号: H01L29/786

    摘要: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译: 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体,该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面,其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。