公开(公告)号：US5636160A

公开(公告)日：1997-06-03

申请号：US570575

申请日：1995-12-11

申请人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

发明人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/16

摘要： A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.

摘要翻译： 一种非易失性半导体存储器，具有：具有以矩阵形式设置的非易失性存储单元的存储单元阵列，每个存储单元具有浮置栅极，控制栅极，擦除栅极，源极和漏极以及被写入的数据 通过将电子注入浮栅并通过从浮栅去除电子而被擦除; 以及由高电压电源和低电压电源驱动的外围电路，分别向控制栅极施加预定电压，分别对每个存储单元擦除栅极和漏极以进入数据写入模式，数据擦除模式和数据之一 读取模式，在数据写入模式下，高电压被施加到要被数据写入的存储单元的控制栅极和漏极，应力松弛电压被施加到不被数据写入的存储器单元的每个擦除栅极，以及 应力松弛电压是高电源和低电源电压之间的中间电压。

公开(公告)号：US5592001A

公开(公告)日：1997-01-07

申请号：US626148

申请日：1996-04-05

申请人： Masamichi Asano

发明人： Masamichi Asano

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/349 ,  G11C11/5621 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/3495

摘要： There is disclosed a non-volatile semiconductor memory device wherein a pair of memory cells constituting one bit data memory unit are connected to a data line in a manner that their drains are commonly connected. When compared to the case where drains of two memory cells are respectively connected to different data lines, the number of the connecting portions between drains and data lines is reduced and the area required for connection is lessened. Thus, a semiconductor memory device satisfactorily miniaturized from the viewpoint of practical use is provided. Further, since there is employed an arrangement such that the one bit data memory unit is comprised of two (a pair of) memory cells, the reliability can be improved. Individual select transistors may be arranged between the drain common junctions in the pair of memory cells, respectively, or a common select transistor may be arranged therebetween. In addition, the sources of the two memory cells may be respectively formed as individual sources.

摘要翻译： 公开了一种非易失性半导体存储器件，其中构成一位数据存储器单元的一对存储单元以其漏极共同连接的方式连接到数据线。 当与两个存储单元的排水口分别连接到不同的数据线的情况相比，排水管和数据线之间的连接部分的数量减少，并且连接所需的面积减小。 因此，提供了从实用性的观点出发令人满意地小型化的半导体存储器件。 此外，由于采用一位数据存储单元由两个（一对）存储单元组成的布置，因此可以提高可靠性。 各个选择晶体管可以分别布置在一对存储单元中的漏极公共接头之间，或者可以在其间布置公共选择晶体管。 此外，两个存储单元的源可以分别形成为各个源。

公开(公告)号：US5519654A

公开(公告)日：1996-05-21

申请号：US450135

申请日：1995-05-25

申请人： Hideo Kato ,  Masamichi Asano ,  Shinji Saito ,  Shigeru Matsuda

发明人： Hideo Kato ,  Masamichi Asano ,  Shinji Saito ,  Shigeru Matsuda

IPC分类号： G11C5/00 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  G11C16/06

CPC分类号： G11C16/30 ,  G11C16/10 ,  G11C16/12

摘要： A semiconductor memory device having a memory cell array with a plurality of transistors (memory cells MC) disposed in a matrix form capable of electrically altering data. In writing data to a plurality of memory cells (MC), a write voltage (V.sub.pp ') is applied to the plurality of memory cells (MC) from a plurality of write circuits (7). The write voltage is generated by boosting an internal voltage (V.sub.CC) by a charge pump circuit (21). In writing data, one of the following methods is used. The plurality of write circuits (7) are sequentially activated by a write control circuit (20) at intervals of delayed timings. The operating point of each memory cell (transistor)(MC) is controlled by operating point control means so as to reduce a current. A capacitor is connected to the output side of the charge pump circuit, and a boosted write voltage is supplied via the capacitor to the write circuit.

摘要翻译： 一种具有存储单元阵列的半导体存储器件，所述存储单元阵列具有以能够电变化数据的矩阵形状的多个晶体管（存储单元MC）。 在向多个存储单元（MC）写入数据时，从多个写入电路（7）向多个存储单元（MC）施加写入电压（Vpp'）。 通过由电荷泵电路（21）升压内部电压（VCC）来产生写入电压。 在编写数据时，使用以下方法之一。 多个写入电路（7）以延迟定时的间隔由写入控制电路（20）依次启动。 每个存储单元（晶体管）（MC）的工作点由工作点控制装置控制，以减少电流。 电容器连接到电荷泵电路的输出侧，并且经由电容器将升压的写入电压提供给写入电路。

公开(公告)号：US5371702A

公开(公告)日：1994-12-06

申请号：US27489

申请日：1993-03-05

申请人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano ,  Kazuhisa Kanazawa ,  Toshio Yamamura

发明人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano ,  Kazuhisa Kanazawa ,  Toshio Yamamura

IPC分类号： G11C16/16 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C16/16

摘要： In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held. As a result, the erasure operation is achieved for all the batch erase blocks corresponding to the erase information holding sections in each of which the erase information data is held, so that a plurality of batch erase blocks can be erased simulataneously, thus reducing the erasure time, as compared with the prior art memory device.

摘要翻译： 响应于从外部依次输入的多个地址信号，擦除信息输入部分控制与待擦除的批量擦除块相对应的擦除信息保持部分，以便保存擦除信息数据。 通过依次重复该操作，擦除信息数据被存储在与要擦除的多批擦除块相对应的擦除信息保持部分中。 接着，基于存储在擦除信息保持部中的擦除信息数据，块消除部分被激活，以擦除保持擦除信息数据的每个相应块的所有非易失性存储器单元。 结果，对于与保持擦除信息数据的擦除信息保持部分相对应的所有批量擦除块实现擦除操作，使得可以同时擦除多个批量擦除块，从而减少擦除 与现有技术的存储器件相比。

公开(公告)号：US5153684A

公开(公告)日：1992-10-06

申请号：US734109

申请日：1991-07-24

申请人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

发明人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0425 ,  H01L27/115

摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.

摘要翻译： 在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。 在基板的源极和漏极区域上形成第一绝缘膜。 在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。 在第二绝缘膜上形成浮栅。 在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。 在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。 在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。 浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。 偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。 第一绝缘膜和杂质区用作存储单元的元件隔离区。

公开(公告)号：US4970686A

公开(公告)日：1990-11-13

申请号：US396246

申请日：1989-08-21

申请人： Yasuo Naruke ,  Thoru Mochizuki ,  Taira Iwase ,  Masamichi Asano

发明人： Yasuo Naruke ,  Thoru Mochizuki ,  Taira Iwase ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C17/12 ,  G11C17/14 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/785 ,  G11C17/12

摘要： A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is inserted between a series node of the FETs and a write data line. The fuse is molten when data is written to the spare memory cell. By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line, the fusing FET is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET to cut off the fuse, thus writing data to the spare memory cell.

公开(公告)号：US20070279112A1

公开(公告)日：2007-12-06

申请号：US10589428

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0818

摘要： A semiconductor memory using a DLL circuit having a phase comparison circuit for comparing phases of an internal clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched to a logic “1” by start of one clock cycle of the internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting the duration time of the logic “1” of the first signal inputted by the variable delay addition circuit through the dummy delay until one clock cycle of the internal clock is completed and setting the initial value of delay amount of the variable delay addition circuit based on the duration time.

摘要翻译： 使用具有用于比较内部时钟和延迟时钟的相位的相位比较电路的DLL电路的半导体存储器和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括：用于输入第一信号的装置 通过在突发开始时的虚拟延迟，将内部时钟的一个时钟周期的开始锁存到逻辑“1”，并通过第一信号的逻辑“1”的持续时间检测装置 通过可变延迟加法电路通过虚拟延迟输入，直到内部时钟的一个时钟周期完成，并根据持续时间设定可变延迟加法电路的延迟量的初始值。

公开(公告)号：US5732022A

公开(公告)日：1998-03-24

申请号：US812765

申请日：1997-03-06

申请人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

发明人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

IPC分类号： G11C8/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C16/00

CPC分类号： G11C16/345 ,  G11C16/16 ,  G11C16/28 ,  G11C16/344 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C8/08 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004

摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.

公开(公告)号：US5576994A

公开(公告)日：1996-11-19

申请号：US428060

申请日：1995-04-25

申请人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

发明人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

IPC分类号： G11C8/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C16/345 ,  G11C16/16 ,  G11C16/28 ,  G11C16/344 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C8/08 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004

摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.

摘要翻译： 当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。 在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。 在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在 打开内存单元。 差分放大器用于检测列线的电位变化。 在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平 例如，各个单元的正方向。 通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。 此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问， 与常规装置相比。

公开(公告)号：US5384742A

公开(公告)日：1995-01-24

申请号：US30343

申请日：1993-03-25

申请人： Tadashi Miyakawa ,  Masamichi Asano

发明人： Tadashi Miyakawa ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/16 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418

摘要： A memory cell array is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another block (non-selected block) to moderate stress between the floating gate and source/drain, thereby preventing write error and erase error. In the program operation, the source and drain of a memory cell in the non-selected block are equalized to moderate an electric field between the control gate and source/drain and not to flow a channel current, thereby preventing write error. In carrying out a negative voltage erase method, prior to setting the source line and word line of a cell in a non-selected block to an erase voltage, the source and word lines are equalized. The equalization operation is released after the erase operation, thereby preventing malfunction of a non-selected cell.

摘要翻译： PCT No.PCT / JP91 / 01272 Sec。 371日期1993年3月25日 102（e）1993年3月25日PCT 1991年9月25日PCT公布。 出版物WO92 / 05560 日期：1992年4月2日。存储单元阵列被分成多个块。 在更改块（选择块）的数据时，将调节电压施加到另一个块（未选择块）中的存储单元的源极或控制栅极，以缓和浮动栅极和源极/漏极之间的应力，从而防止写入 错误和擦除错误。 在编程操作中，未选择的块中的存储单元的源极和漏极被均衡以控制控制栅极和源极/漏极之间的电场，并且不流过沟道电流，从而防止写入错误。 在执行负电压擦除方法时，在将未选块中的单元的源极线和字线设置为擦除电压之前，源极和字线被均衡。 在擦除操作之后释放均衡操作，从而防止未选择的单元的故障。