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    Memory cells and methods of forming memory cells
    63.
    发明授权
    Memory cells and methods of forming memory cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US09496495B2

    公开(公告)日：2016-11-15

    申请号：US15176609

    申请日：2016-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Martin Schubert ,  Shu Qin ,  Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy ,  Allen McTeer ,  Yongjun Jeff Hu

    IPC: H01L21/20 ,  H01L45/00

    CPC classification number: H01L45/1608 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

    Abstract: Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. The memory cell also has a switching material over and directly against the intermediate material, an ion reservoir material over the switching material, and a second electrode over the ion reservoir material. Some embodiments include methods of forming memory cells.

    Abstract translation: 一些实施例包括具有第一电极的存储器单元，以及在第一电极之上并直接抵靠第一电极的中间材料。 中间材料包括对应于碳和硼之一或两者的稳定物质。 存储单元还具有超过并直接抵靠中间材料的开关材料，开关材料上方的离子储存器材料以及离子储存器材料上的第二电极。 一些实施例包括形成存储器单元的方法。

    Methods of forming transistor gates
    64.
    发明授权
    Methods of forming transistor gates 有权
    形成晶体管栅极的方法

    公开(公告)号：US09396952B2

    公开(公告)日：2016-07-19

    申请号：US14225053

    申请日：2014-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/792

    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

    Abstract translation: 一些实施例包括形成电荷存储晶体管栅极和标准FET栅极的方法，其中公共处理用于制造不同类型栅极的至少一些部分。 可以形成FET和电荷存储晶体管栅极堆叠。 栅极堆叠可以各自包括栅极材料，绝缘材料和牺牲材料。 牺牲材料从FET中去除并对存储晶体管栅极堆叠进行充电。 FET栅极堆叠的绝缘材料被蚀刻通过。 导电材料形成在FET栅叠层上方和电荷存储晶体管栅堆上。 导电材料物理地接触FET栅极堆叠的栅极材料，并且通过残留在电荷存储晶体管栅极堆叠中的绝缘材料与电荷存储晶体管栅极堆叠的栅极材料分离。 一些实施例包括门结构。

    Phase change memory stack with treated sidewalls
    65.
    发明授权
    Phase change memory stack with treated sidewalls 有权
    具有处理侧壁的相变存储器堆叠

    公开(公告)号：US09281471B2

    公开(公告)日：2016-03-08

    申请号：US14266365

    申请日：2014-04-30

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu ,  Tsz W. Chan ,  Swapnil Lengade ,  Everett Allen McTeer ,  Shu Qin

    IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.

    Abstract translation: 已经公开了用于制造存储器件的存储器件和方法。 一种这样的存储器件包括形成在字线材料上的第一电极材料。 在第一电极材料上形成选择器装置材料。 第二电极材料形成在选择器装置材料上。 在第二电极材料上形成相变材料。 在相变材料上形成第三电极材料。 粘附物质是等离子体掺杂到存储器堆叠的侧壁中，并且衬垫材料形成在存储器堆叠的侧壁上。 粘附物质与存储器堆叠和侧壁衬套的元件混合以终止元件和侧壁衬套的不满足的原子键。

    Methods of forming doped regions in semiconductor substrates
    68.
    发明授权
    Methods of forming doped regions in semiconductor substrates 有权
    在半导体衬底中形成掺杂区的方法

    公开(公告)号：US09093367B2

    公开(公告)日：2015-07-28

    申请号：US13929590

    申请日：2013-06-27

    Applicant: Micron Technology, Inc.

    Inventor： Lequn Jennifer Liu ,  Shu Qin ,  Allen McTeer ,  Yongjun Jeff Hu

    IPC: H01L21/26 ,  H01L21/42 ,  H01L21/223 ,  H01L21/265 ,  H01L29/66

    CPC classification number: H01L21/2236 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26526 ,  H01L29/66575

    Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

    Abstract translation: 一些实施例包括在半导体衬底中形成一个或多个掺杂区域的方法。 可以使用等离子体掺杂来形成第一掺杂剂到衬底内的第一深度。 然后可以用第二掺杂剂冲击第一掺杂剂以将第一掺杂剂敲入衬底内的第二深度。 在一些实施方案中，第一掺杂剂是p型（例如硼），第二掺杂剂是中性型（例如锗）。 在一些实施方案中，第二掺杂剂比第一掺杂剂重。

    Interconnects and semiconductor devices including at least two portions of a metal nitride material and methods of fabrication
    69.
    发明授权
    Interconnects and semiconductor devices including at least two portions of a metal nitride material and methods of fabrication 有权
    包括金属氮化物材料的至少两部分和制造方法的互连和半导体器件

    公开(公告)号：US08835274B2

    公开(公告)日：2014-09-16

    申请号：US14043536

    申请日：2013-10-01

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu

    IPC: H01L29/92 ,  H01L29/94 ,  H01L21/74 ,  H01L49/02 ,  H01L27/108 ,  H01L21/768

    CPC classification number: H01L29/945 ,  H01L21/743 ,  H01L21/76846 ,  H01L21/76847 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.

    Abstract translation: 金属 - 绝缘体 - 金属电容器，其具有包括金属氮化物材料的至少两部分的底部电极。 金属氮化物材料的至少一部分包括与另一部分不同的材料。 还公开了包括金属氮化物材料的至少两部分的互连件，金属氮化物材料的至少一部分由与金属氮化物材料的另一部分不同的材料形成。 还公开了制造这种MIM电容器和互连的方法，以及包括这种MIM电容器和互连的半导体器件。

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