公开(公告)号：US6099935A

公开(公告)日：2000-08-08

申请号：US573469

申请日：1995-12-15

申请人： William Brearley ,  Laertis Economikos ,  Paul F. Findeis ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Arthur Gilman Merryman ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  James Patrick Wood ,  Roy Yu

发明人： William Brearley ,  Laertis Economikos ,  Paul F. Findeis ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Arthur Gilman Merryman ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  James Patrick Wood ,  Roy Yu

IPC分类号： H01L21/60 ,  H01L21/68 ,  H05K3/34 ,  B23K31/02

CPC分类号： H01L24/81 ,  H01L21/6835 ,  H01L24/75 ,  H05K3/3484 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/11003 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11472 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/742 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/043 ,  Y10T428/24174 ,  Y10T428/24273 ,  Y10T428/24479

摘要： An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position. The depth is appropriate to facilitate wettingly attracting the solder material to the facing IO land when the apparatus is in the manufacturing position and the semiconductor device and the apparatus are exposed to appropriate ambient conditions to effect reflow of the solder material. The invention also includes a method for using the apparatus in manufacturing a semiconductor device.

摘要翻译： 一种用于制造半导体器件的装置，其具有以IO阵列布置在IO面上的输入 - 输出（IO）焊盘，该主体具有从操作面延伸到主体中的多个空腔; 空腔被布置在空腔轨迹阵列中，当该设备处于制造位置时，其中操作面大体上邻近IO面，该腔轨迹阵列与IO凸台对齐。 每个空腔具有深度和横向宽度，其协作以建立由空腔底部和至少一个空腔壁限定的体积。 当装置处于制造位置时，体积容纳适当量的焊料材料以建立在面对的IO焊盘上的焊料材料的量度。 当装置处于制造位置时，该深度适于促进将焊料材料润湿地吸引到相对的IO焊盘，并且半导体器件和设备暴露于适当的环境条件以实现焊料材料的回流。 本发明还包括一种在制造半导体器件中使用该装置的方法。

公开(公告)号：US6057216A

公开(公告)日：2000-05-02

申请号：US987076

申请日：1997-12-09

申请人： Laertis Economikos ,  Cheruvu S. Murthy ,  Hua Shen

发明人： Laertis Economikos ,  Cheruvu S. Murthy ,  Hua Shen

IPC分类号： H01L21/225 ,  H01L21/334 ,  H01L21/822 ,  H01L23/00 ,  H01L27/04 ,  H01L29/94 ,  H01L21/38

CPC分类号： H01L29/66181 ,  H01L21/2255 ,  H01L29/945 ,  Y10S438/92

摘要： Doped semiconductor with high dopant concentrations in small semiconductor regions without excess spreading of the doped region are formed by:(a) applying a dopant-containing oxide glass layer on the semiconductor surface,(b) capping the dopant-containing oxide glass layer with a conformal silicon oxide layer,(c) heating the substrate from step (b) in a non-oxidizing atmosphere whereby at least a portion of the dopant in the glass diffuses into the substrate at the semiconductor surface, and(d) heating the glass-coated substrate from step (c) in an oxidizing atmosphere whereby at least a portion of the dopant in the glass near the semiconductor surface is forced into the substrate at the semiconductor surface by diffusion of oxygen through the glass.The method is especially useful for making buried plates in semiconductor substrates which may be used in trench capacitor structures. The preferred semiconductor substrate material is monocrystalline silicon. The preferred dopant is arsenic.

摘要翻译： 通过：（a）在半导体表面上施加含掺杂剂的氧化物玻璃层，（b）用含有掺杂剂的氧化物玻璃层将掺杂剂氧化物玻璃层盖上 （c）在非氧化气氛中加热来自步骤（b）的衬底，由此玻璃中的至少一部分掺杂剂在半导体表面扩散到衬底中，（d）加热玻璃 - 在步骤（c）中，在半导体表面附近的玻璃中的掺杂剂的至少一部分通过氧气扩散通过玻璃而被迫进入到半导体表面的衬底中。 该方法对于将半导体衬底中的掩模板制成可用于沟槽电容器结构中是特别有用的。 优选的半导体衬底材料是单晶硅。 优选的掺杂剂是砷。

公开(公告)号：US5534371A

公开(公告)日：1996-07-09

申请号：US446355

申请日：1995-05-22

申请人： Rajesh S. Patel ,  Laertis Economikos

发明人： Rajesh S. Patel ,  Laertis Economikos

IPC分类号： G03F1/20 ,  G03F1/54 ,  G03F1/72 ,  G03F9/00

CPC分类号： G03F1/72 ,  G03F1/54 ,  G03F1/20 ,  Y10S430/146

摘要： A repaired laser ablation mask is disclosed capable of withstanding laser fluences in the range from about 200 mJ/cm.sup.2 to at least 500 mJ/cm.sup.2. The repaired mask comprises a single or multiple layers of apertured metal, such as, aluminum, on a quartz substrate. The laser mask repair technique and structure are also disclosed. The thickness of the metal layer, such as, aluminum layer, is in the range from about 2 microns to about 6 microns. A laser projection etching technique is also disclosed for using the repaired ablation mask.

摘要翻译： 所公开的修复的激光烧蚀掩模能够承受在约200mJ / cm 2至至少500mJ / cm 2范围内的激光能量密度。 被修复的掩模包括在石英衬底上的单层或多层有孔金属，例如铝。 还公开了激光掩模修复技术和结构。 金属层（例如铝层）的厚度在约2微米至约6微米的范围内。 还公开了使用修复的消融掩模的激光投影蚀刻技术。

公开(公告)号：US09607864B2

公开(公告)日：2017-03-28

申请号：US13479087

申请日：2012-05-23

申请人： John H. Zhang ,  Laertis Economikos ,  Wei-Tsu Tseng ,  Adam Ticknor

发明人： John H. Zhang ,  Laertis Economikos ,  Wei-Tsu Tseng ,  Adam Ticknor

IPC分类号： H01L21/02 ,  H01L21/67 ,  B01D24/00 ,  B01D53/82

CPC分类号： H01L21/67017 ,  B01D15/362 ,  B01D15/363 ,  B01D24/002 ,  B01D24/008 ,  B01D53/82 ,  B01D2201/287 ,  B01D2221/14 ,  B01D2253/206 ,  B01D2258/0216 ,  H01L21/6704 ,  H01L21/67051

摘要： The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

公开(公告)号：US08822994B2

公开(公告)日：2014-09-02

申请号：US13615368

申请日：2012-09-13

申请人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

发明人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

IPC分类号： H01L23/58 ,  H01L29/10 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L24/05 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

摘要翻译： 一种方法，其包括在衬底上形成第一电平的有源电路，形成电连接到所述第一电平有源电路的第一探针焊盘，其中所述第一探针焊盘具有第一表面，所述第一探针焊盘与所述第一探针焊盘接触， 所述第一探针焊盘的位于所述第一表面上方的部分，以及在所述第一探针焊盘上执行化学机械抛光，以在所述第一表面上方平坦化所述第一探针焊盘的所述部分。 该方法还包括形成覆盖在第一探针焊盘上的第二电平有源电路，形成电连接到第二电平有源电路的第二探针焊盘，使第二探针焊盘与移位探针焊盘的一部分的探针尖接触， 以及化学机械地抛光第二探针垫以除去所移动的部分。

公开(公告)号：US20130312791A1

公开(公告)日：2013-11-28

申请号：US13479087

申请日：2012-05-23

申请人： John H. Zhang ,  Laertis Economikos ,  Wei-Tsu Tseng ,  Adam Ticknor

发明人： John H. Zhang ,  Laertis Economikos ,  Wei-Tsu Tseng ,  Adam Ticknor

IPC分类号： B08B3/14

CPC分类号： H01L21/67017 ,  B01D15/362 ,  B01D15/363 ,  B01D24/002 ,  B01D24/008 ,  B01D53/82 ,  B01D2201/287 ,  B01D2221/14 ,  B01D2253/206 ,  B01D2258/0216 ,  H01L21/6704 ,  H01L21/67051

摘要： The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

摘要翻译： 本公开涉及在半导体处理期间使用的流体过滤系统和方法。 一个或多个实施例涉及当流体被提供到半导体晶片处理工具（例如半导体晶片清洁工具）时从流体中过滤离子和颗粒的流体过滤系统和方法。

公开(公告)号：US20130072011A1

公开(公告)日：2013-03-21

申请号：US13619616

申请日：2012-09-14

申请人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

发明人： John H. Zhang ,  Laertis Economikos ,  Robin Van Den Nieuwenhuizen ,  Wei-Tsu Tseng

IPC分类号： H01L21/768

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L24/05 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

公开(公告)号：US08117568B2

公开(公告)日：2012-02-14

申请号：US12237727

申请日：2008-09-25

申请人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

发明人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5009 ,  G06F2217/12 ,  Y02P90/265

摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

摘要翻译： 方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的 之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。

公开(公告)号：US20110195640A1

公开(公告)日：2011-08-11

申请号：US12702333

申请日：2010-02-09

申请人： Glenn L. Cellier ,  Laertis Economikos ,  Timothy M. McCormack ,  Rajasekhar Venigalla

发明人： Glenn L. Cellier ,  Laertis Economikos ,  Timothy M. McCormack ,  Rajasekhar Venigalla

IPC分类号： B24B1/00 ,  B24B7/20 ,  B24B37/00

CPC分类号： B24B37/16 ,  B24B37/22 ,  B24B37/245

摘要： A chemical mechanical polishing (CMP) system includes a rotating polishing table including a platen providing at least two pressure zones having different pressures; a sub-pad positioned on the platen, the sub-pad including a plurality of openings allowing for transmission of the different pressures therethrough; a fixed abrasive pad positioned on the sub-pad; and a pressure-creating system sealingly coupled to the platen for creating a different pressure in the at least two pressure zones, wherein the different pressures create topography on the fixed abrasive pad. A sub-pad and related method are also provided.

摘要翻译： 化学机械抛光（CMP）系统包括旋转抛光台，其包括提供具有不同压力的至少两个压力区的压板; 位于所述压板上的子垫，所述子垫包括允许通过其传递不同压力的多个开口; 定位在子垫上的固定磨料垫; 以及密封地联接到所述压板的压力产生系统，用于在所述至少两个压力区域中产生不同的压力，其中所述不同压力在所述固定磨料垫上产生形貌。 还提供了一个子垫和相关方法。

公开(公告)号：US20100077372A1

公开(公告)日：2010-03-25

申请号：US12237727

申请日：2008-09-25

申请人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

发明人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/12 ,  Y02P90/265

摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

摘要翻译： 方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的 之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。