公开(公告)号：US20200043548A1

公开(公告)日：2020-02-06

申请号：US16541239

申请日：2019-08-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA

IPC: G11C11/419 ,  G11C7/14 ,  G11C7/22 ,  G11C16/04 ,  G11C16/24 ,  G11C16/28 ,  H01L27/11529 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4099 ,  H01L29/786

Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.

公开(公告)号：US20190377401A1

公开(公告)日：2019-12-12

申请号：US16476642

申请日：2018-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei MAEDA ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Kiyoshi KATO

IPC: G06F1/3234 ,  G11C5/14 ,  G11C16/30 ,  G11C14/00

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

公开(公告)号：US20190189622A1

公开(公告)日：2019-06-20

申请号：US16275380

申请日：2019-02-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H01L27/115 ,  H01L29/24 ,  G11C11/24 ,  H01L27/06 ,  H01L27/1156 ,  H01L29/786 ,  G11C11/408 ,  G11C11/403 ,  G11C8/14 ,  G11C7/16 ,  H01L27/11551

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-1th sub memory cell.[Selected Drawing] FIG. 8

公开(公告)号：US20180114578A1

公开(公告)日：2018-04-26

申请号：US15784495

申请日：2017-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/28

Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.

公开(公告)号：US20170243874A1

公开(公告)日：2017-08-24

申请号：US15591150

申请日：2017-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H01L27/115 ,  H01L29/24 ,  G11C11/24 ,  H01L29/786

CPC classification number: H01L27/115 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/24 ,  H01L29/7869

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≧2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20170236842A1

公开(公告)日：2017-08-17

申请号：US15430746

申请日：2017-02-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinpei MATSUDA ,  Masayuki SAKAKURA ,  Yuki HATA ,  Shuhei NAGATSUKA ,  Yuta ENDO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1222 ,  H01L27/1225 ,  H01L27/1237 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with high design flexibility is provided. A first transistor and a second transistor having electrical characteristics different from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. For example, semiconductor materials with different electron affinities are used for a semiconductor layer in which a channel of the first transistor is formed and a semiconductor layer in which a channel of the second transistor is formed. This allows the threshold voltages of the first transistor and the second transistor to differ from each other. Forming a gate electrode using a damascene process enables miniaturization and high density of the transistors. Furthermore, a highly-integrated semiconductor device is provided.

公开(公告)号：US20160336051A1

公开(公告)日：2016-11-17

申请号：US15220469

申请日：2016-07-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei NAGATSUKA ,  Yasuyuki TAKAHASHI

IPC: G11C7/22 ,  H01L27/105 ,  H01L29/786 ,  H01L27/12 ,  G11C8/10 ,  G11C5/06

CPC classification number: G11C7/22 ,  G11C5/06 ,  G11C8/10 ,  G11C11/404 ,  G11C16/02 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/7869

Abstract: A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.

Abstract translation: 具有新颖结构的半导体存储装置，即使在未提供电力（即非易失性）的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。 半导体存储装置包括存储单元阵列，其中多个存储单元以矩阵形式排列;解码器，被配置为根据控制信号选择存储单元在多个存储单元之间进行操作;以及控制电路， 选择是否将控制信号输出到解码器。 在多个存储单元的每一个中，通过关闭其沟道区域形成有氧化物半导体的选择晶体管来保持数据。

公开(公告)号：US20150263008A1

公开(公告)日：2015-09-17

申请号：US14643621

申请日：2015-03-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA

IPC: H01L27/108

CPC classification number: H01L27/1156 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/405 ,  G11C11/4085 ,  H01L27/11551 ,  H01L27/1225

Abstract: A novel semiconductor device that can write and read multilevel data is provided. A memory cell includes a bit line, a power supply line, first and second nodes, first to fourth transistors, and first and second capacitors. One of two divided multilevel data is written to the first node through the first transistor. The other of the divided multilevel data is written to the second node through the second transistor. A gate of the third transistor is connected to the first node, and a gate of the fourth transistor is connected to the second node. The third and fourth transistors control electrical continuity between the bit line and the power supply line. Each of the first and second transistors preferably includes an oxide semiconductor in a semiconductor layer.

Abstract translation: 提供了一种可以写入和读取多级数据的新型半导体器件。 存储单元包括位线，电源线，第一和第二节点，第一至第四晶体管以及第一和第二电容器。 两个分割的多电平数据之一通过第一晶体管写入第一节点。 分割的多级数据中的另一个通过第二晶体管写入第二节点。 第三晶体管的栅极连接到第一节点，并且第四晶体管的栅极连接到第二节点。 第三和第四晶体管控制位线和电源线之间的电连续性。 第一和第二晶体管中的每一个优选地包括半导体层中的氧化物半导体。

公开(公告)号：US20130335056A1

公开(公告)日：2013-12-19

申请号：US13908121

申请日：2013-06-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Kiyoshi KATO ,  Shuhei NAGATSUKA ,  Koichiro KAMATA ,  Tsutomu MURAKAWA ,  Takahiro TSUJI ,  Kaori IKADA

IPC: G05F3/16

CPC classification number: G05F3/16 ,  G05F1/56 ,  G05F3/242

Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

Abstract translation: 本发明的一个目的是提供一种具有改善的噪声容限的调节器电路。 在包括基于第一电源端子和第二电源端子之间的电位差产生参考电压的偏置电路的调节器电路中，以及基于参考电位向输出端子输出电位的电压调节器 在偏置电路的输入端，在电源端子与偏置电路中包含的晶体管的栅极连接的节点之间设置有旁路电容器。