公开(公告)号：US09786350B2

公开(公告)日：2017-10-10

申请号：US14208714

申请日：2014-03-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru

IPC: G11C14/00 ,  G11C11/24 ,  G11C11/403 ,  H01L27/12 ,  H01L27/1156

CPC classification number: G11C11/24 ,  G11C11/403 ,  G11C14/0054 ,  G11C2207/007 ,  H01L27/1156 ,  H01L27/1225

Abstract: A memory device with a novel structure that is suitable for a register file is provided. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit includes a first logic element and a second logic element each of which is configured to perform logic inversion, a selection circuit, a first switch, a second switch, and a third switch. The second memory circuit includes a first transistor in which a channel formation region is provided in an oxide semiconductor film, a second transistor, and a capacitor to which a potential is supplied through the first transistor.

公开(公告)号：US09601215B2

公开(公告)日：2017-03-21

申请号：US14676923

申请日：2015-04-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru

IPC: G11C19/18 ,  H03K17/00 ,  H01L27/12 ,  H01L29/24 ,  H03K19/00 ,  H03K3/356 ,  G11C11/405 ,  G11C11/24 ,  G11C14/00 ,  G11C11/412

CPC classification number: G11C19/184 ,  G11C11/24 ,  G11C11/405 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696 ,  H03K3/356008 ,  H03K17/005 ,  H03K19/0016

Abstract: A holding circuit includes first to third input terminals, an output terminal, first to third switches, a capacitor, and a node. The first to third switches control conduction between the node and the first input terminal, conduction between the node and the output terminal, and conduction between the second input terminal and the output terminal, respectively. First and second terminals of the capacitor are electrically connected to the node and the third input terminal, respectively. The first to third switches are each a transistor comprising an oxide semiconductor layer comprising a semiconductor region. Owing to the structure, a potential change of the node in an electrically floating state can be suppressed; thus, the holding circuit can retain its state for a long time. The holding circuit can be used as a memory circuit for backup of a sequential circuit, for example.

公开(公告)号：US09472680B2

公开(公告)日：2016-10-18

申请号：US14636611

申请日：2015-03-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda ,  Takuro Ohmaru

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/06 ,  H01L27/12 ,  H01L29/04 ,  H01L27/088

CPC classification number: H01L27/1251 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/045 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor. Note that the second gate electrode not only controls the threshold voltages (Vth) of the first transistor and the second transistor but also has an effect of reducing interference of an electric field applied from respective first gate electrodes of the first transistor and the second transistor.

公开(公告)号：US09312851B2

公开(公告)日：2016-04-12

申请号：US14731606

申请日：2015-06-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Hidetomo Kobayashi

IPC: H01L25/00 ,  H01L27/108 ,  H01L27/12 ,  H01L27/115 ,  H03K3/012 ,  H03K3/356 ,  G11C5/00 ,  H03K17/687 ,  G11C5/14 ,  G11C11/403 ,  G11C11/4076

CPC classification number: H03K17/687 ,  G11C5/005 ,  G11C5/148 ,  G11C11/403 ,  G11C11/4076 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1207 ,  H03K3/012 ,  H03K3/356008

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

公开(公告)号：US09293186B2

公开(公告)日：2016-03-22

申请号：US14208428

申请日：2014-03-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Naoaki Tsutsui ,  Atsuo Isobe ,  Wataru Uesugi ,  Takuro Ohmaru

IPC: G11C11/24 ,  G11C11/401 ,  G11C11/403

CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。

公开(公告)号：US09202567B2

公开(公告)日：2015-12-01

申请号：US14318841

申请日：2014-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru

IPC: G11C14/00 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/115 ,  H01L27/12 ,  G11C5/14 ,  G11C11/34 ,  G11C11/41 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C14/0018 ,  G11C5/14 ,  G11C11/34 ,  G11C11/41 ,  G11C14/00 ,  G11C14/0063 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1207 ,  H01L29/788 ,  H01L29/792

Abstract: The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory section, a transistor whose channel is formed in an oxide semiconductor layer allows a signal to be held in the capacitor for a long period. Thus, the memory circuit can hold a logic state (data signal) even while the power supply is stopped. A potential applied to a gate of the transistor whose channel is formed in an oxide semiconductor layer is raised by a booster circuit provided between a wiring for carrying power supply potential and the gate of the transistor, allowing a data signal to be held even by one power supply potential without malfunction.

Abstract translation: 本发明提供了一种存储电路，其中在不提供电力的情况下，已经保存在与易失性存储器相对应的存储器部分中的数据信号可以被保存在与非易失性存储器相对应的存储器部分中的电容器中。 在非易失性存储器部分中，其沟道形成在氧化物半导体层中的晶体管允许信号被长时间保持在电容器中。 因此，即使在电源停止的情况下，存储电路也可以保持逻辑状态（数据信号）。 施加到其沟道形成在氧化物半导体层中的晶体管的栅极的电位由设置在用于承载电源电位的布线和晶体管的栅极之间的升压电路升高，允许数据信号被保持为一个 电源电位无故障。

公开(公告)号：US09190172B2

公开(公告)日：2015-11-17

申请号：US14157574

申请日：2014-01-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Naoaki Tsutsui

IPC: G11C8/16 ,  G11C29/00 ,  G01R31/3185

CPC classification number: G11C29/00 ,  G01R31/318597

Abstract: To supply a signal in which the occurrence of delays is prevented to a storage circuit. To provide a novel semiconductor device in which a load applied to a logic circuit is low. The following structure is completed: a storage circuit to which a plurality of data signals and a selection signal are supplied connects two combination circuits, and a storage circuit has a function of selecting one of a plurality of data signals in accordance with the selection signal. A selection circuit is not necessarily provided between the storage circuit and the combination circuit. As a result, the combination circuit can supply a signal in which the occurrence of delays is prevented to the storage circuit.

Abstract translation: 提供一种信号，其中阻止发生延迟到存储电路。 提供一种新颖的半导体器件，其中施加到逻辑电路的负载较低。 完成以下结构：提供多个数据信号和选择信号的存储电路连接两个组合电路，并且存储电路具有根据选择信号选择多个数据信号中的一个的功能。 在存储电路和组合电路之间不一定设置选择电路。 结果，组合电路可以向存储电路提供阻止发生延迟的信号。

公开(公告)号：US09076520B2

公开(公告)日：2015-07-07

申请号：US14333576

申请日：2014-07-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru

IPC: G11C14/00 ,  G11C11/404 ,  H01L21/84 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/12 ,  G11C11/24 ,  G11C16/04 ,  H01L29/786

CPC classification number: G11C14/0018 ,  G11C11/24 ,  G11C11/404 ,  G11C16/0416 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/115 ,  H01L27/1156 ,  H01L27/1203 ,  H01L29/7869

Abstract: The storage device includes a volatile first memory circuit and a nonvolatile second memory circuit which includes a transistor whose channel is formed in an oxide semiconductor layer. In the case of high-frequency driving, during a period when source voltage is applied, a data signal is input to and output from the first memory circuit, and during a part of a period when source voltage is supplied, which is before the supply of the source voltage is stopped, a data signal is input to the second memory circuit. In the case of low-frequency driving, during a period when source voltage is applied, a data signal is input to the second memory circuit, the data signal input to the second memory circuit is input to the first memory circuit, and the data signal input to the first memory circuit is output.

Abstract translation: 存储装置包括易失性第一存储器电路和非易失性第二存储器电路，其包括其通道形成在氧化物半导体层中的晶体管。 在高频驱动的情况下，在施加电源电压的期间，数据信号被输入到第一存储电路并从第一存储电路输出，并且在供给源电压的期间的一部分期间 的源电压停止，数据信号被输入到第二存储电路。 在低频驱动的情况下，在施加电源电压的期间，将数据信号输入到第二存储电路，输入到第二存储电路的数据信号输入到第一存储电路，数据信号 输出到第一存储器电路的输入。

公开(公告)号：US20150070064A1

公开(公告)日：2015-03-12

申请号：US14541305

申请日：2014-11-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masami Endo ,  Takuro Ohmaru

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/356008 ,  H03K3/012 ,  H03K21/023 ,  H03K21/403

Abstract: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Abstract translation: 提供一种可以切换到静止状态并且可以从静止状态快速返回的集成电路。 提供一种能够在不降低运行速度的情况下降低功耗的集成电路。 提供了一种用于驱动集成电路的方法。 集成电路包括第一触发器和包括非易失性存储器电路的第二触发器。 在提供电力的操作状态下，第一触发器保持数据。 在停止供电的静止状态下，第二触发器保持数据。 在从操作状态转变到静止状态时，数据从第一触发器传送到第二触发器。 从静止状态返回到工作状态时，数据从第二触发器传送到第一触发器。

公开(公告)号：US08786311B2

公开(公告)日：2014-07-22

申请号：US14060020

申请日：2013-10-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Yutaka Shionoiri

IPC: H03K19/177 ,  H01L29/786

CPC classification number: H01L27/105 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17772

Abstract: A programmable analog device in which data can be held even when supply of a power supply potential is stopped. The programmable circuit includes unit cells connected in parallel or in series, and each of the unit cells includes an analog element. A conduction state of each of the unit cells is changed between an on state and an off state. Each of the unit cells includes, as a switch of the unit cell, a first transistor having a sufficiently low off-state current and a second transistor, a gate electrode of the second transistor being electrically connected to a source or drain electrode of the first transistor. The conduction state of the unit cell is controlled with a potential of the gate electrode of the second transistor, which can be kept even when no power is supplied thanks to the low off-state current of the first transistor.

Abstract translation: 即使停止供给电源电位，也可以进行数据保持的可编程模拟装置。 可编程电路包括并联或串联连接的单位单元，并且每个单位单元包括模拟元件。 每个单电池的导通状态在导通状态和断开状态之间变化。 每个单电池包括作为单位电池的开关的具有足够低的截止电流的第一晶体管和第二晶体管，第二晶体管的栅电极电连接到第一晶体管的源电极或漏电极 晶体管。 单电池的导通状态由第二晶体管的栅电极的电位来控制，即使在没有供电的情况下，由于第一晶体管的低截止电流也可以保持该电位。