利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

177 条记录 (耗时 0.028 秒)

    Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion
    62.
    发明申请
    Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion 有权

    公开(公告)号：US20150194334A1

    公开(公告)日：2015-07-09

    申请号：US14662743

    申请日：2015-03-19

    申请人： International Business Machines Corporation

    发明人： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-chen Yeh

    IPC分类号： H01L21/762

    CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L29/517 ,  H01L29/7846

    摘要： A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.

    INDEPENDENT GATE VERTICAL FINFET STRUCTURE
    63.
    发明申请
    INDEPENDENT GATE VERTICAL FINFET STRUCTURE 有权
    独立栅栏垂直FINFET结构

    公开(公告)号：US20150187867A1

    公开(公告)日：2015-07-02

    申请号：US14141600

    申请日：2013-12-27

    申请人： International Business Machines Corporation

    发明人： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/06 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

    摘要： A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A first gate channel is formed between a first source/drain junction formed in the substrate and a second source/drain junction formed in the first semiconductor fin. A first gate stack is formed on sidewalls of the first gate channel. A first spacer is interposed between the first gate stack and the first source/drain junction.

    摘要翻译： 半导体器件包括沿第一方向延伸以限定衬底长度的衬底和垂直于第一方向的第二方向以限定衬底宽度。 第一半导体鳍形成在基板的上表面上。 第一半导体鳍片沿着第二方向以第一距离延伸以限定第一鳍片宽度。 第一栅极沟道形成在形成在衬底中的第一源极/漏极结和形成在第一半导体鳍中的第二源极/漏极结之间。 第一栅极堆叠形成在第一栅极沟道的侧壁上。 第一间隔物置于第一栅叠层和第一源极/漏极结之间。

    PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS
    65.
    发明申请
    PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS 有权
    部分隔离的精细形状场效应晶体管

    公开(公告)号：US20140264603A1

    公开(公告)日：2014-09-18

    申请号：US14036759

    申请日：2013-09-25

    申请人： International Business Machines Corporation

    发明人： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

    IPC分类号： H01L27/12

    CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545

    摘要： A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates.

    摘要翻译： 一种用于形成鳍状场效应晶体管（FinFET）器件的晶体管器件和方法，其中鳍状物的沟道部分在掩埋的氧化硅上，而硅片上的鳍片的源极和漏极部分。 一种示例性方法包括接收具有通过掩埋氧化物（BOX）层与硅衬底电隔离的硅层的晶片。 BOX层与硅层和硅衬底物理接触。 该方法还包括在硅衬底中注入阱并在阱之间形成垂直源和漏极。 垂直的源极和漏极延伸穿过BOX层，鳍片和一部分虚拟栅极。

    Preventing Fin erosion and limiting EPI overburden in FinFET structures by composite hardmask
    66.
    发明授权
    Preventing Fin erosion and limiting EPI overburden in FinFET structures by composite hardmask 有权
    通过复合硬掩模防止鳍片侵蚀并限制FinFET结构中的EPI覆盖层

    公开(公告)号：US08815670B2

    公开(公告)日：2014-08-26

    申请号：US14017488

    申请日：2013-09-04

    申请人： International Business Machines Corporation

    发明人： Veeraraghavan S. Basker ,  Effendi Leobandung ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged.

    摘要翻译： 通过在绝缘层上包含含硅层的衬底上形成硬掩模层来形成FinFET结构。 硬掩模层包括含硅层上的第一层，第二层和第三层。 翅片阵列由硬掩模层和含硅层形成。 形成盖子，其覆盖翅片阵列中的每一个的一部分而不是全部长度。 该部分覆盖阵列中的每个翅片。 门限定栅极两侧的源/漏区。 隔离件形成在栅极的每一侧上，形成间隔物以进行以从源极/漏极区域中的鳍片的部分去除第三层。 硬掩模层的第二层从源极/漏极区域中的鳍片的部分去除，并且源极/漏极区域中的鳍片被合并。

    FINFET WITH MERGE-FREE FINS
    67.
    发明申请
    FINFET WITH MERGE-FREE FINS 审中-公开
    FINFET具有无缝FINS

    公开(公告)号：US20140167162A1

    公开(公告)日：2014-06-19

    申请号：US13713842

    申请日：2012-12-13

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Chun-chen Yeh ,  Yunpeg Yin

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

    摘要： A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

    摘要翻译： 半导体器件包括绝缘层，形成在绝缘层的上表面上的有源半导体层和形成在绝缘层上的多个鳍。 翅片形成在第一源极/漏极区域和第二源极/漏极区域之间的栅极和间隔区域中，而不延伸到第一和第二源极/漏极区域中。

    Stacked nanowire field effect transistor
    68.
    发明授权
    Stacked nanowire field effect transistor 有权
    叠层纳米线场效应晶体管

    公开(公告)号：US08679902B1

    公开(公告)日：2014-03-25

    申请号：US13628726

    申请日：2012-09-27

    申请人： International Business Machines Corporation

    发明人： Veeraraghavan S. Basker ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC分类号： H01L21/335

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439

    摘要： A method for fabricating a nanowire field effect transistor device includes depositing a first sacrificial layer on a substrate, depositing a first layer of a semiconductor material on the first sacrificial layer, depositing a second sacrificial layer on the first layer of semiconductor material, depositing a second layer of the semiconductor material on the second sacrificial layer, pattering and removing portions of the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer, patterning a dummy gate stack, removing the dummy gate stack, removing portions of the sacrificial layer to define a first nanowire including a portion of the first semiconductor layer and a second nanowire including a portion of the second semiconductor layer, and forming gate stacks about the first nanowire and the second nanowire.

    摘要翻译： 一种制造纳米线场效应晶体管器件的方法包括在衬底上沉积第一牺牲层，在第一牺牲层上沉积半导体材料的第一层，在第一半导体材料层上沉积第二牺牲层， 在第二牺牲层上的半导体材料的层，对第一牺牲层，第一半导体层，第二牺牲层和第二半导体层的部分进行图案化和去除，图案化虚拟栅极堆叠，去除伪栅极堆叠，去除 牺牲层的部分以限定包括第一半导体层的一部分的第一纳米线和包括第二半导体层的一部分的第二纳米线，以及围绕第一纳米线和第二纳米线形成栅极堆叠。

    Contact formation through low-tempearature epitaxial deposition in semiconductor devices
    70.
    发明授权
    Contact formation through low-tempearature epitaxial deposition in semiconductor devices 有权

    公开(公告)号：US10804270B2

    公开(公告)日：2020-10-13

    申请号：US15787011

    申请日：2017-10-18

    申请人： International Business Machines Corporation

    发明人： Oleg Gluschenkov ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L21/24 ,  H01L21/283 ,  H01L21/02 ,  H01L21/8238

    摘要： A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.