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    Forming a characterization parameter of a resistive memory element
    61.
    发明授权
    Forming a characterization parameter of a resistive memory element 有权
    形成电阻式存储元件的表征参数

    公开(公告)号：US09105360B2

    公开(公告)日：2015-08-11

    申请号：US13789123

    申请日：2013-03-07

    Applicant: Seagate Technology LLC

    Inventor： Ryan James Goss ,  Mark Allen Gaertner ,  Antoine Khoueir ,  David Scott Ebsen ,  Jon D. Trantham

    IPC: G06F12/00 ,  G11C29/50 ,  G06F11/10 ,  G11C13/00

    CPC classification number: G11C29/50008 ,  G06F11/10 ,  G06F11/1012 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2013/0092

    Abstract: An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed.

    Abstract translation: 定义增量信号，其包括持续时间和峰值电压中的至少一个小于电阻式存储器元件的相应的最小编程时间或最小编程电压阶跃。 重复执行表征过程，其至少包括：将信号施加到存储元件，在每个随后的应用期间，信号由增量信号递增; 响应于所述信号测量所述存储元件的第一电阻; 以及c）在没有施加编程信号的第一电阻的测量经过一段时间之后测量存储元件的第二电阻。 响应于表征过程的第一和第二电阻测量，形成存储元件的表征参数。

    PARTIAL REPROGRAMMING OF SOLID-STATE NON-VOLATILE MEMORY CELLS
    63.
    发明申请
    PARTIAL REPROGRAMMING OF SOLID-STATE NON-VOLATILE MEMORY CELLS 有权
    固态非挥发性记忆细胞的部分重现

    公开(公告)号：US20150023097A1

    公开(公告)日：2015-01-22

    申请号：US13943441

    申请日：2013-07-16

    Applicant: Seagate Technology LLC

    Inventor： Antoine Khoueir ,  Varun Voddi ,  Rodney Virgil Bowman

    IPC: G11C7/00 ,  G11C16/14 ,  G11C16/10 ,  G11C16/04 ,  G11C13/00

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3431

    Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the programmed state of a selected memory cell in the set is detected, and the selected memory cell is partially reprogrammed to return the selected memory cell to the associated initial programmed state.

    Abstract translation: 用于管理诸如闪存阵列的存储器中的数据的方法和装置。 根据一些实施例，将数据写入一组固态非易失性存储器单元，使得该组中的每个存储单元被写入相关联的初始编程状态。 检测到集合中所选择的存储器单元的编程状态的漂移，并且所选存储单元被部分重新编程以使所选择的存储单元返回到相关的初始编程状态。

    Data Update Management in a Cloud Computing Environment
    64.
    发明申请
    Data Update Management in a Cloud Computing Environment 审中-公开
    云计算环境中的数据更新管理

    公开(公告)号：US20140244896A1

    公开(公告)日：2014-08-28

    申请号：US13777810

    申请日：2013-02-26

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Ryan James Goss ,  David Scott Ebsen ,  Mark Allen Gaertner ,  Michael Joseph Steiner ,  Antoine Khoueir

    IPC: G06F3/06

    CPC classification number: G06F3/067 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0649 ,  G06F3/0685

    Abstract: Method and apparatus for managing data in a cloud computing environment. In accordance with some embodiments, data updates are received to a multi-tier memory structure across a cloud network and stored as working data in an upper rewritable non-volatile memory tier of the memory structure. The working data are periodically logged to a lower non-volatile memory tier in the memory structure while a current version of the working data remain in the upper memory tier. The upper and lower memory tiers each are formed of rewritable memory cells having different constructions and storage attributes.

    Abstract translation: 用于在云计算环境中管理数据的方法和装置。 根据一些实施例，数据更新被接收到跨云网络的多层存储器结构，并作为工作数据存储在存储器结构的上部可重写非易失性存储器层中。 工作数据被定期地记录到存储器结构中的较低的非易失性存储器层，而当前版本的工作数据保留在上层存储器层中。 上层和下层记忆层每个由具有不同构造和存储属性的可重写存储单元形成。

    DATA PROTECTION FOR UNEXPECTED POWER LOSS
    65.
    发明申请
    DATA PROTECTION FOR UNEXPECTED POWER LOSS 审中-公开
    数据保护意外的电力损失

    公开(公告)号：US20140219021A1

    公开(公告)日：2014-08-07

    申请号：US13761965

    申请日：2013-02-07

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Jon D. Trantham ,  Michael Joseph Steiner ,  Antoine Khoueir

    IPC: G11C5/14

    CPC classification number: G11C5/143 ,  G11C7/24 ,  G11C11/005

    Abstract: A data storage device receives a write data command and data. The data is stored in a buffer of the data storage device. The data storage device issues a command complete status indication. After the command complete status indication is issued, the data are stored in a primary memory of the data storage device. The primary memory comprises a first type of non-volatile memory and the buffer comprises a second type of non-volatile memory that is different from the first type of non-volatile memory.

    Abstract translation: 数据存储装置接收写数据命令和数据。 数据存储在数据存储装置的缓冲器中。 数据存储设备发出命令完成状态指示。 在发出命令完成状态指示之后，将数据存储在数据存储设备的主存储器中。 主存储器包括第一类型的非易失性存储器，并且缓冲器包括与第一类型的非易失性存储器不同的第二类型的非易失性存储器。

    MEMORY WITH SEPARATE READ AND WRITE PATHS
    67.
    发明申请
    MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
    具有单独读取和写入数据的存储器

    公开(公告)号：US20130188419A1

    公开(公告)日：2013-07-25

    申请号：US13785525

    申请日：2013-03-05

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    IPC: G11C11/16

    CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

    Abstract translation: 存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。 巨磁电阻单元包括自由磁性层。 磁性隧道结数据单元电耦合在读取位线和读取源极线之间。 磁性隧道结数据单元包括自由磁性层。 写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。 磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

    Mitigation of solid state memory read failures with peer based thresholds
    70.
    发明授权
    Mitigation of solid state memory read failures with peer based thresholds 有权

    公开(公告)号：US11080129B2

    公开(公告)日：2021-08-03

    申请号：US16729228

    申请日：2019-12-27

    Applicant: Seagate Technology LLC

    Inventor： Mehmet Emin Aklik ,  Antoine Khoueir ,  Darshana H. Mehta ,  Nicholas Lien

    IPC: G06F11/07

    Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.

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