公开(公告)号：US07344924B1

公开(公告)日：2008-03-18

申请号：US11136925

申请日：2005-05-24

申请人： Chuan-Cheng Cheng ,  Shuhua Yu ,  Roawen Chen ,  Albert Wu

发明人： Chuan-Cheng Cheng ,  Shuhua Yu ,  Roawen Chen ,  Albert Wu

IPC分类号： H01L21/82

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

摘要翻译： 保险丝结构，包括该结构的集成电路，以及使用该保险丝的结构和（重新）配置电路的方法。 熔丝结构通常包括（a）具有至少两个电耦合到其上的电路元件的导电结构，（b）导电结构上的电介质层，和（c）第一介电层和导电结构上的第一透镜， 以至少部分地将光聚焦到导电结构上。 制造该结构的方法通常包括以下步骤：（1）形成电耦合到第一和第二电路元件的导电结构，（2）在其上形成介电层，和（3）在电介质层上或之上形成透镜， 在导电结构之上，透镜被配置为至少部分地将光聚焦到导电结构上。 （重新）配置电路的方法通常包括以下步骤：（i）在电路表面上或附近照射足够的电气断开位于透镜下方的对应的第一保险丝的至少一个透镜，并且禁用电路的第一配置 ，以及（ii）在该电路表面上或其附近照射至少一个其他透镜，足以使位于该透镜下方的对应的第二保险丝电气断开并使电路能够进行第二配置。 该结构和方法有利地提供具有改善的可靠性和更小的芯片面积的熔丝结构，从而提高制造工艺的产量和每个晶片的模具数量（总和良好）。

公开(公告)号：US20070183173A1

公开(公告)日：2007-08-09

申请号：US11348367

申请日：2006-02-07

申请人： Albert Wu

发明人： Albert Wu

IPC分类号： H02J1/10

CPC分类号： H02M3/157

摘要： A voltage regulator provides a regulated output load voltage at either a positive level or an inverted level relative to an input supply voltage. A switching circuit and control circuit are formed on an integrated circuit having a single pin for coupling to regulator feedback signal. The feedback signal is applied directly to the feedback pin during both positive voltage level regulation and inverted voltage level regulation. The feedback signal may be produced by a feedback circuit comprising an impedance element formed in the integrated circuit.

摘要翻译： 电压调节器提供相对于输入电源电压处于正电平或反相电平的稳压输出负载电压。 开关电路和控制电路形成在具有用于耦合到调节器反馈信号的单个引脚的集成电路上。 在正电压电平调节和反相电压调节期间，反馈信号直接施加到反馈引脚。 反馈信号可以由包括在集成电路中形成的阻抗元件的反馈电路产生。

公开(公告)号：US20070145957A1

公开(公告)日：2007-06-28

申请号：US11316993

申请日：2005-12-27

申请人： Albert Wu ,  Steven Pietkiewicz

发明人： Albert Wu ,  Steven Pietkiewicz

IPC分类号： G05F1/00

CPC分类号： H02M3/1563 ,  H02M2001/0032 ,  H02M2001/0035 ,  Y02B70/16

摘要： A converter coupled to a DC voltage input and connectable to a load, includes a signal responsive switch coupled between a first circuit point and a second circuit point. In lieu of burst mode operation during low load conditions, the peak switch current is varied directly with load condition and a switch deactivation interval is varied inversely with load condition. The switch deactivation level is within a maximum level to avoid audio frequency band interference, while maintaining high efficiency operation throughout the load range.

摘要翻译： 耦合到DC电压输入并可连接到负载的A转换器包括耦合在第一电路点和第二电路点之间的信号响应开关。 代替低负载条件下的突发模式操作，峰值开关电流随负载状态直接变化，开关停用间隔与负载条件反向变化。 开关去激活电平处于最大电平以避免音频频带干扰，同时在整个负载范围内保持高效率运行。

公开(公告)号：US20070053250A1

公开(公告)日：2007-03-08

申请号：US11162131

申请日：2005-08-30

申请人： Albert Wu

发明人： Albert Wu

IPC分类号： G11B21/08 ,  G11B7/24

CPC分类号： G06F1/187 ,  G06F1/181

摘要： This invention is a mass storage system based on laser disc technology. While there are various laser discs players available, they are all aimed at serving an audio/visual entertainment purpose with no consideration given to the ability of this type of media to service the vast amount of data created in the information age. This invention will help users manage a vast laser disc collection, secure all information through backup, and make volumetric data truly portable.

摘要翻译： 本发明是基于激光盘技术的海量存储系统。 虽然有各种激光光盘播放器可用，但它们都是为了服务于音视频娱乐目的，没有考虑到这种类型的媒体能够服务于在信息时代创建的大量数据。 本发明将帮助用户管理庞大的激光光盘集合，通过备份保护所有信息，并使体积数据真正便携。

公开(公告)号：US20070030713A1

公开(公告)日：2007-02-08

申请号：US11347791

申请日：2006-02-03

申请人： Steven Pietkiewicz ,  Albert Wu

发明人： Steven Pietkiewicz ,  Albert Wu

IPC分类号： H02M7/02

CPC分类号： H02M3/33507 ,  H02M3/335 ,  H02M3/3385 ,  H05B41/30

摘要： The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

摘要翻译： 本发明提供一种对容性负载进行充电的电容器充电电路。 特别地，电路和技术优选地被提供用于使用来自变压器的初级和次级绕组的电流来控制开关的导通时间和关断时间。 这种布置优选地产生适应性的导通时间和适应性关断时间开关，其能够快速地从低至零伏至几百伏的电容器负载充电。 优选间接测量输出电压以防止不必要的功率消耗。 此外，一旦达到期望的输出电压，可以提供控制电路来节省电力以停止向电容器负载的电力输送。 控制电路优选地操作询问定时器，周期性地启动功率传递周期，以将电容器输出负载维持在恒定的准备状态。

公开(公告)号：US5986934A

公开(公告)日：1999-11-16

申请号：US977647

申请日：1997-11-24

申请人： Dah-Bin Kao ,  Loc B. Hoang ,  Albert Wu ,  Tung-Yi Chan

发明人： Dah-Bin Kao ,  Loc B. Hoang ,  Albert Wu ,  Tung-Yi Chan

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/28

摘要： A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

摘要翻译： 本文提供了一种半导体存储器阵列及其方法，包括：衬底; 多个存储单元场效应晶体管，形成在所述基板上并被布置在晶体管的行和列中，每个晶体管包括介于漏极和源极区之间并由控制栅极区重叠的沟道区; 形成在所述基板内的多个第一扩散细长区域，其共同地将各个晶体管的漏极区域电连接; 形成在所述衬底内的多个第二扩散细长区域，其共同地将各个晶体管的源极区域电连接; 以及形成在所述衬底上的多个细长导电线，其共同地电连接相应行中的晶体管的控制栅极区域。

公开(公告)号：US5373465A

公开(公告)日：1994-12-13

申请号：US132942

申请日：1993-10-07

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  G11C11/34 ,  G11C7/00

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

公开(公告)号：US5317179A

公开(公告)日：1994-05-31

申请号：US764019

申请日：1991-09-23

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68 ,  H01L29/34 ,  H01L29/78

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

摘要翻译： 公开了使用片上电压倍增器电路仅需要5伏外部源的闪速EEPROM单元，以提供在编程和擦除模式期间实现Fowler-Nordheim隧穿所需的高电压。 浮置栅极和控制栅极之间以及浮置栅极和漏极区域之间的介电层的性质不同，以便于浮动栅极的编程和擦除。 还公开了一种通过在浮动栅极和控制栅极之间形成绝缘层以使电容低于浮置栅极和漏极区域之间的绝缘层的电容的电容来产生快闪EEPROM单元的方法。

公开(公告)号：US08987830B2

公开(公告)日：2015-03-24

申请号：US12943673

申请日：2010-11-10

申请人： Shiann-Ming Liou ,  Albert Wu

发明人： Shiann-Ming Liou ,  Albert Wu

IPC分类号： H01L27/11 ,  H01L23/50 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/50 ,  H01L24/11 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/16 ,  H01L2224/11334 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16268 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19104 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了一种方法，包括在半导体管芯的表面上形成导电结构，将半导体管芯附接到基板，形成模制化合物以封装半导体管芯，在模制化合物中形成开口， 至少部分地暴露导电结构，并且通过模制化合物中的开口将无源部件电耦合到导电结构。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08861214B1

公开(公告)日：2014-10-14

申请号：US11932733

申请日：2007-10-31

申请人： Albert Wu ,  Chuan-Cheng Cheng

发明人： Albert Wu ,  Chuan-Cheng Cheng

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： H01L25/16 ,  H01L2224/04042 ,  H01L2224/16265 ,  H01L2224/32265 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Substrates for integrated passive devices are described herein. Embodiments of the present invention provide substrates including a glass layer and at least one passive device disposed thereon. According to various embodiments of the present invention, the glass layer may have a thickness adapted to minimize conductive and/or other interactions between the substrate and the at least one passive device. Other embodiments may be described and claimed.

摘要翻译： 本文描述了用于集成无源器件的衬底。 本发明的实施例提供了包括玻璃层和设置在其上的至少一个无源器件的衬底。 根据本发明的各种实施例，玻璃层可以具有适于最小化衬底和至少一个无源器件之间的导电和/或其它相互作用的厚度。 可以描述和要求保护其他实施例。