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    Signal Converter Circuit, Display Device, and Electronic Device
    64.
    发明申请
    Signal Converter Circuit, Display Device, and Electronic Device 有权
    信号转换器电路，显示装置和电子装置

    公开(公告)号：US20130162613A1

    公开(公告)日：2013-06-27

    申请号：US13716885

    申请日：2012-12-17

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kazunori Watanabe ,  Hiroyuki Miyake

    IPC: H03K17/04 ,  G09G5/00

    CPC classification number: H03K17/04 ,  G09G3/3648 ,  G09G3/3688 ,  G09G3/3696 ,  G09G5/001

    Abstract: To suppress an adverse effect of change in held data in a sample-and-hold circuit as a result of increase in operation speed on a generated parallel data signal. A signal converter circuit includes a first sample-and-hold circuit and a second sample-and-hold circuit each of which has a function of extracting and holding part of a serial data signal as a data in accordance with a sampling control signal and has a function of generating a data signal which is one of data signals of a parallel data signal by using the held data and outputting the data signal. The second sample-and-hold circuit includes a switch which has a function of selecting whether the potential of the data of the second sample-and-hold circuit is set to a reference potential or not in accordance with the sampling control signal of the first sample-and-hold circuit.

    Abstract translation: 由于对所生成的并行数据信号的操作速度的增加，抑制在采样保持电路中的保持数据变化的不利影响。 信号转换器电路包括第一采样保持电路和第二采样保持电路，每个采样保持电路具有根据采样控制信号提取和保持串行数据信号的一部分作为数据的功能，并具有 通过使用保持的数据产生作为并行数据信号的数据信号之一的数据信号并输出​​数据信号的功能。 第二采样保持电路包括开关，其具有根据第一采样保持电路的采样控制信号选择第二采样保持电路的数据的电位是否被设置为参考电位的功能 采样保持电路。

    DISPLAY DEVICE
    65.
    发明申请
    DISPLAY DEVICE 有权
    显示设备

    公开(公告)号：US20130162609A1

    公开(公告)日：2013-06-27

    申请号：US13718402

    申请日：2012-12-18

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroyuki Miyake ,  Kouhei Toyotaka ,  Kazunori Watanabe ,  Toru Tanabe ,  Makoto Kaneyasu ,  Masashi Fujita

    IPC: G09G3/20

    CPC classification number: G09G3/20 ,  G09G2370/08

    Abstract: To provide a display device with high image quality and fewer terminals. The present invention is made with a focus on the positional relation between a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit. The structure conceived is such that a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit are provided close to each other so that an RC load between the serial-parallel conversion circuit and the external connection terminal is reduced

    Abstract translation: 提供具有高图像质量和更少终端的显示设备。 本发明的重点是串行并行转换电路和用于向串行 - 并行转换电路提供串行信号的外部连接端子之间的位置关系。 所构想的结构使得串行并行转换电路和用于向串行 - 并行转换电路提供串行信号的外部连接端子彼此靠近地设置，使得串行 - 并行转换电路和外部电路之间的RC负载 连接端子减少

    PULSE SIGNAL OUTPUT CIRCUIT AND SHIFT REGISTER
    66.
    发明申请
    PULSE SIGNAL OUTPUT CIRCUIT AND SHIFT REGISTER 有权
    脉冲信号输出电路和移位寄存器

    公开(公告)号：US20130135023A1

    公开(公告)日：2013-05-30

    申请号：US13754959

    申请日：2013-01-31

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Hiroyuki Miyake

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  G09G3/20 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2330/021 ,  G11C19/28 ,  H03K19/096

    Abstract: A pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit are provided. A clock signal is supplied to one of transistors connected to a first output terminal. A power supply potential is applied to one of transistors connected to a second output terminal. Thus, power consumed by discharge and charge of the transistor included in the second output terminal can be reduced. Further, since a potential is supplied from a power source to the second output terminal, sufficient charge capability can be obtained.

    Abstract translation: 提供能够稳定运行的脉冲信号输出电路和包括脉冲信号输出电路的移位寄存器。 时钟信号被提供给连接到第一输出端子的晶体管之一。 电源电位施加到连接到第二输出端子的晶体管之一。 因此，可以减少包括在第二输出端子中的晶体管的放电和电荷所消耗的功率。 此外，由于从电源向第二输出端子提供电位，因此可以获得足够的充电能力。

    Semiconductor device
    68.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12199106B2

    公开(公告)日：2025-01-14

    申请号：US18197785

    申请日：2023-05-16

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Kouhei Toyotaka ,  Jun Koyama ,  Hiroyuki Miyake

    IPC: G11C19/00 ,  G02F1/1334 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/36 ,  G11C19/28 ,  H01L27/12 ,  H01L29/786 ,  G09G3/3266 ,  G09G3/3275

    Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

    Memory device and semiconductor device
    69.
    发明授权
    Memory device and semiconductor device 有权

    公开(公告)号：US12193244B2

    公开(公告)日：2025-01-07

    申请号：US17891248

    申请日：2022-08-19

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yutaka Shionoiri ,  Hiroyuki Miyake ,  Kiyoshi Kato

    IPC: H01L29/786 ,  H01L27/12 ,  H01L27/13 ,  H10B41/70 ,  H10B69/00 ,  H10B99/00 ,  G11C16/04

    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

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