公开(公告)号：US06906366B2

公开(公告)日：2005-06-14

申请号：US10441661

申请日：2003-05-20

申请人： Sheng Teng Hsu ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Fengyan Zhang

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4983 ,  H01L21/02189 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28291 ,  H01L21/31053 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/78391

摘要： A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

摘要翻译： 提供了具有铁电栅极和高k绝缘体的铁电晶体管栅极结构。 高k绝缘体可以用作栅极电介质和绝缘体，以减少或消除氧或氢扩散到铁电栅极中。 还提供了形成铁电栅极结构的方法。 该方法包括以下步骤：形成牺牲栅极结构，去除牺牲栅极结构，沉积高k绝缘体，沉积铁电材料，使用CMP抛光铁电材料，以及形成覆盖铁电材料的顶部电极。

公开(公告)号：US06774004B1

公开(公告)日：2004-08-10

申请号：US10391357

申请日：2003-03-17

申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang ,  Wei Pan ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang ,  Wei Pan ,  Fengyan Zhang

IPC分类号： H01L2120

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1683

摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.

摘要翻译： 制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。 交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

公开(公告)号：US06720258B2

公开(公告)日：2004-04-13

申请号：US10319313

申请日：2002-12-12

申请人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2144

CPC分类号： H01L21/28518 ,  H01L29/456

摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

摘要翻译： 集成电路器件及其制造方法包括在（100）Si上的外延硅化镍，或者由钴中间层制造的在非晶Si上的稳定的硅化镍。 在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积钴（Co）界面层。 钴中间层通过由钴中间层与镍和硅的反应形成的钴/镍/硅合金层调节Ni原子的通量，使得Ni原子以相似的速率到达Si界面，即没有 任何取向偏好，从而形成均匀的硅化镍层。 可以将镍硅化物退火以形成均匀的结晶二硅化镍。 因此，实现了（100）Si或非晶Si上的单晶硅化镍，其中硅化镍具有改进的稳定性并可用于超浅结结器件中。

公开(公告)号：US06682995B2

公开(公告)日：2004-01-27

申请号：US10317742

申请日：2002-12-11

申请人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L213205

CPC分类号： H01L29/456 ,  H01L21/28291 ,  H01L28/55 ,  H01L28/65

摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

摘要翻译： 已经提供了具有高温稳定性的导电阻挡层，其可用作铁电电容器电极。 该导电屏障允许在涉及退火的IC工艺中使用铱（Ir）金属。 已经发现，分离硅衬底与Ir膜与中间相邻的钽（Ta）膜非常有效地抑制层之间的扩散。 Ir防止退火过程中氧进入硅的相互扩散。 Ta或TaN层防止Ir扩散到硅中。 这种Ir / TaN结构保护了硅界面，从而使粘附，电导，小丘和剥离问题最小化。 使用覆盖Ir / TaN结构的Ti也有助于防止退火过程中的小丘形成。 还提供了形成多层Ir导电结构和Ir铁电电极的方法。

公开(公告)号：US06190963B1

公开(公告)日：2001-02-20

申请号：US09316661

申请日：1999-05-21

申请人： Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

发明人： Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55

摘要： An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir—M—O composite film barrier layer and an Ir—M—O composite film ferroelectric electrode are also provided.

摘要翻译： 已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜在氧气环境中耐高温退火。 当与由相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/屏障结构可用于非易失性FeRAM器件，DRAM，电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件。 还提供了形成Ir-M-O复合膜阻挡层和Ir-M-O复合膜铁电电极的方法。

公开(公告)号：US08242482B2

公开(公告)日：2012-08-14

申请号：US12042983

申请日：2008-03-05

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff

IPC分类号： H01L31/072

CPC分类号： H05B33/145

摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

摘要翻译： 提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。 该方法包括：用纳米尖端形成底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。 纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。 通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。 在一个方面，Si磷光体层是SRSO层。 响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

公开(公告)号：US20080197399A1

公开(公告)日：2008-08-21

申请号：US11707712

申请日：2007-02-16

申请人： Sheng Teng Hsu ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Fengyan Zhang

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L29/94 ,  B82Y10/00 ,  H01L28/91 ,  H01L29/66083

摘要： A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by forming a thin layer of dielectric overlying the nanotips using an atomic layer deposition (ALD) process. In one aspect, the electrically insulating dielectric covering the nanotips forms a three-dimensional interface of dielectric-covered nanotips. Then, the electrically conductive top electrode overlying the dielectric-covered nanotips forms a three-dimensional top electrode interface, matching the first three-dimensional interface of the dielectric-covered nanotips.

摘要翻译： 提供了一种纳米尖端电容器和相关联的制造方法。 该方法提供底部电极并且生长覆盖底部电极的导电的纳米技术。 沉积覆盖在纳米尖端上的电绝缘电介质，并且将导电顶部电极沉积在覆盖有电介质的纳米尖端上。 通常，通过使用原子层沉积（ALD）工艺形成覆盖在纳米尖端上的介电层的薄层来沉积电介质。 在一个方面，覆盖纳米尖端的电绝缘电介质形成介电覆盖的纳米尖端的三维界面。 然后，覆盖介电覆盖的纳米尖端的导电顶部电极形成三维顶部电极接口，与介电覆盖的纳米尖端的第一个三维界面相匹配。

公开(公告)号：US20080096345A1

公开(公告)日：2008-04-24

申请号：US11580623

申请日：2006-10-12

申请人： Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01G9/00 ,  H01L21/8242

CPC分类号： H01G9/07 ,  Y10S977/762 ,  Y10T29/417

摘要： A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the nanowire shells. A main cavity is formed between the top electrode and bottom electrodes, partially displaced by a first plurality of nanowire shells. Electrolyte cavities are formed between the sleeves and nanowires by etching the first sacrificial layer. In one aspect, electrolyte cavities are formed between the bottom electrode top surface and a shell coating layer joining the sleeve bottom openings. Then, the main and electrolyte cavities are filled with either a liquid or gas phase electrolyte. In a different aspect, the first sacrificial layer is a solid phase electrolyte that is not etched away.

摘要翻译： 提供了形成纳米电化学（NEC）电池的方法。 该方法提供了具有顶部表面的底部电极。 形成纳米线贝壳。 每个纳米线壳具有纳米线和套管，纳米线连接到底部电极顶表面。 顶部电极形成在纳米线壳上。 在顶部电极和底部电极之间形成主要腔室，部分地被第一多个纳米线壳体置换。 通过蚀刻第一牺牲层，在套筒和纳米线之间形成电解质空腔。 在一个方面，在底部电极顶表面和连接套筒底部开口的外壳涂层之间形成电解质腔。 然后，主要和电解质空腔填充有液相或气相电解质。 在不同的方面，第一牺牲层是不被蚀刻掉的固相电解质。

公开(公告)号：US20080092955A1

公开(公告)日：2008-04-24

申请号：US11582197

申请日：2006-10-16

申请人： Fengyan Zhang ,  Robert A. Barrowcliff ,  Gregory M. Stecker ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Robert A. Barrowcliff ,  Gregory M. Stecker ,  Sheng Teng Hsu

IPC分类号： H01L31/00

CPC分类号： H01G9/2031 ,  H01G9/2059 ,  H01L51/0036 ,  H01L51/0086 ,  H01L51/4226 ,  Y02E10/542

摘要： A method of fabricating a photovoltaic cell for use in a solar cell structure includes preparing a first substrate; preparing a TiO2 precursor; preparing a cold wall CVD chamber; placing the first substrate in the cold wall CVD chamber; forming a transparent conducting electrode on the first substrate; depositing a porous column TiO2 film on the transparent conducting electrode; depositing a photosensitive material in and on the porous column TiO2 film; forming a top electrode on the photovoltaic cell; and incorporating the photovoltaic cell into a solar cell structure. The method of the invention is suitable for forming photovoltaic cells which may be of the dye-sensitized solar cell (DSSC) type, having a liquid or solid-state electrolyte therein, or an ordered organic-inorganic heterojunction photovoltaic cell.

摘要翻译： 制造太阳能电池结构中使用的太阳能电池的方法包括制备第一基板; 制备TiO 2前体; 准备冷壁CVD室; 将第一衬底放置在冷壁CVD室中; 在所述第一基板上形成透明导电电极; 在透明导电电极上沉积多孔柱TiO 2膜; 在多孔色谱柱TiO 2膜上沉积感光材料; 在所述光伏电池上形成顶部电极; 并将光伏电池并入太阳能电池结构中。 本发明的方法适用于形成可能是其中具有液体或固态电解质的染料敏化太阳能电池（DSSC）型或有序无机异质结光伏电池的光伏电池。

公开(公告)号：US07101720B2

公开(公告)日：2006-09-05

申请号：US10801375

申请日：2004-03-15

申请人： Fengyan Zhang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

摘要： A method is provided for forming a single-phase c-axis PGO film overlying a Pt metal electrode. Although the method is summarized in the context of a Pt bottom electrode, it has a broader application to other noble metals. The method comprises: forming a bottom electrode mixture of Pt and Pt3O4; forming a single-phase c-axis PGO thin film overlying the bottom electrode; and, forming a top electrode overlying the PGO thin film. Forming a bottom electrode mixture of a Pt and Pt3O4 includes: forming a Pt first layer; and, forming a second layer, interposed between the first layer and the PGO thin film, of fully oxidized Pt3O4. In other aspects, forming a bottom electrode mixture of Pt and Pt3O4 includes forming a polycrystalline mixture of Pt and Pt3O4. A c-axis PGO film capacitor is also provided. Again, a Pt bottom electrode is described, along with other noble metal bottom electrodes.

摘要翻译： 提供了用于形成覆盖在Pt金属电极上的单相c轴PGO膜的方法。 虽然该方法在Pt底部电极的上下文中总结，但是其更适用于其它贵金属。 该方法包括：形成Pt和Pt 3 O 4的底部电极混合物; 形成覆盖在底部电极上的单相c轴PGO薄膜; 并且形成覆盖PGO薄膜的顶部电极。 形成Pt和Pt 3 N 4 O 4的底部电极混合物包括：形成Pt第一层; 并且形成介于第一层和PGO薄膜之间的完全氧化的Pt 3 O 4 O 4的第二层。 在其它方面，形成Pt和Pt 3 O 4的底部电极混合物包括形成Pt和Pt 3 O 3的多晶混合物 > 4 。 还提供了一个c轴PGO薄膜电容器。 同样地，描述了Pt底部电极以及其它贵金属底部电极。