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    DESIGN STRUCTURES FOR HIGH-VOLTAGE INTEGRATED CIRCUITS
    63.
    发明申请
    DESIGN STRUCTURES FOR HIGH-VOLTAGE INTEGRATED CIRCUITS 失效
    高压集成电路的设计结构

    公开(公告)号：US20090179268A1

    公开(公告)日：2009-07-16

    申请号：US12059034

    申请日：2008-03-31

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    IPC分类号： H01L29/786 ,  G06F17/50

    CPC分类号： H01L27/1203

    摘要： Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.

    摘要翻译： 高压集成电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的设计结构可以包括具有位于第一和第二栅电极之间的半导体本体的器件结构。 第一和第二栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将第一和第二栅极电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，介电材料可与形成其它器件隔离区的工艺同时进行。

    INTEGRATED CIRCUIT PROTECTION DURING HIGH-CURRENT ESD TESTING
    65.
    发明申请
    INTEGRATED CIRCUIT PROTECTION DURING HIGH-CURRENT ESD TESTING 有权
    在高电流ESD测试期间的集成电路保护

    公开(公告)号：US20130271883A1

    公开(公告)日：2013-10-17

    申请号：US13446394

    申请日：2012-04-13

    申请人： Shunhua Chang ,  James Paul Di Sarro ,  Robert J. Gauthier, JR. ,  Nathan Jack ,  Souvick Mitra

    发明人： Shunhua Chang ,  James Paul Di Sarro ,  Robert J. Gauthier, JR. ,  Nathan Jack ,  Souvick Mitra

    IPC分类号： H02H9/04

    CPC分类号： G01R31/002 ,  G01R31/2851 ,  H01L27/0248 ,  H02H9/046 ,  H05K9/0067

    摘要： A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

    摘要翻译： 提供了使用ESD测试系统在静电放电（ESD）测试期间保护集成电路内的器件的方法。 该方法包括将直流（DC）偏置电压施加到集成电路的至少一个器件的输入，并将ESD仿真信号施加到集成电路的至少一个其他输入。 施加的ESD模拟信号沿着第一电流路径传导到第一地，而与至少一个装置相关联的低电流信号沿着第二电流路径传导到第二地。 响应于由所施加的ESD模拟信号产生的第二接地上的信号变化，DC偏置电压在至少一个器件的输入和第二接地之间以基本恒定的值保持。

    SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP
    69.
    发明申请
    SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP 有权
    用于制造集成电路芯片的半导体结构和系统

    公开(公告)号：US20090134463A1

    公开(公告)日：2009-05-28

    申请号：US12348344

    申请日：2009-01-05

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L29/78

    CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

    摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.

    摘要翻译： 一种半导体结构和用于制造集成电路芯片的系统。 半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。 用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。