公开(公告)号：US06333229B1

公开(公告)日：2001-12-25

申请号：US09523839

申请日：2000-03-13

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

IPC分类号： H01L21336

CPC分类号： H01L29/66621 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/7834

摘要： A viable T-gate FET is produced even when the cap of the “T” is mis-aligned from the stem of the “T”. A subtractive etch is used to selectively etch the material forming the cap of the T-gate and the material forming the stem of the T-gate in order to avoid the etching away of portions of the stem if the cap is mis-aligned relative to the stem. To that end, germanium (Ge) may be used as the material for the cap of the T-gate and poly silicon (polySi) may be used as the material for the stem of the T-gate. Since germanium can be etched selectively relative to silicon from 10:1 to as much as 20:1, the cap of the T can be formed without appreciable damage to the stem portion and thus without damage to the resultant FET device.

摘要翻译： 即使当“T”的盖与“T”的杆不对齐时，也会产生可行的T型栅极FET。 使用减法蚀刻来选择性地蚀刻形成T形栅的帽和形成T形栅的杆的材料的材料，以避免如果帽相对于 茎。 为此，可以使用锗（Ge）作为T型栅极的盖的材料，并且可以使用多晶硅（polySi）作为T型栅极的材料。 由于锗可以相对于硅选择性地从10:1蚀刻到多达20:1，所以可以形成T的帽，而不会对柄部产生明显的损害，从而不会损坏所得到的FET器件。

公开(公告)号：US6150256A

公开(公告)日：2000-11-21

申请号：US183338

申请日：1998-10-30

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76825 ,  H01L21/0274 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76811

摘要： The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.

摘要翻译： 本发明提供了一种在微芯片制造期间产生通孔和沟槽的改进方法。 根据本发明，通过使用两层特别选择的抗蚀剂，在光刻工艺期间，通孔和沟槽是自对准的，并且使抗蚀剂曝光，使得下抗蚀剂仅在上抗蚀剂层中形成开口的地方露出。 这种自对准使通孔能够被印制成细长的形状，这允许使用特别有效的图像增强技术。 本发明还提供了一种用于产生通孔和沟槽的简化过程，因为仅需要一个蚀刻步骤来同时产生通孔和沟槽。 本发明的替代实施例允许将被修剪以形成隔离特征的循环或链接的图像，诸如使用图像增强技术印刷的图像。

公开(公告)号：US6007968A

公开(公告)日：1999-12-28

申请号：US959779

申请日：1997-10-29

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： G03F1/00 ,  G03F7/038 ,  G03F7/20 ,  H01L21/027 ,  H01L21/02 ,  G03C5/00

CPC分类号： G03F7/70466 ,  G03F7/038 ,  H01L21/0274 ,  G03F7/2022

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the "loops" formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.

摘要翻译： 本发明的优选实施例通过提供使用混合抗蚀剂形成不连接特征的方法来克服现有技术的局限性。 该方法使用修剪工艺来修剪由混合抗蚀剂形成的“环”的连接特征。 这允许该方法形成多个未链接的特征而不是循环。 为了修剪端部，通过第二曝光步骤或通过利用灰度光罩，形成与窄特征线相邻的相对较大的修整区域。 更宽或更宽的开放区域允许在窄特征线中形成特征并且从相对较大的区域修剪特征，从而导致区域特征而不是环。

公开(公告)号：US5998835A

公开(公告)日：1999-12-07

申请号：US24840

申请日：1998-02-17

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Jack A. Mandelman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Jack A. Mandelman

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L29/50

CPC分类号： H01L29/66613 ,  H01L29/66621 ,  H01L29/7834 ,  H01L21/2255

摘要： A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.

摘要翻译： 一种MOSFET器件及其制造方法。 该器件具有形成在硅衬底中的沟槽。 设备的通道位于沟槽的底部。 扩散层邻近沟槽的相对侧形成。 通过沿着沟槽的侧壁和沟槽的一部分延伸扩散层，将每个扩散层连接到器件沟道的边缘。

公开(公告)号：US07838943B2

公开(公告)日：2010-11-23

申请号：US11161146

申请日：2005-07-25

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

IPC分类号： H01L21/70

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US07601205B2

公开(公告)日：2009-10-13

申请号：US12125442

申请日：2008-05-22

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： B03C3/60

CPC分类号： B03C3/41 ,  B03C3/60 ,  B03C2201/10 ,  Y10S977/742

摘要： An air particle precipitator and a method of air filtration include a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further includes an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further include a metal layer over the carbon nanotube.

摘要翻译： 空气颗粒除尘器和空气过滤方法包括壳体单元; 住房单元中的第一个导体; 壳体单元中的第二导体; 和在第二导体上生长的碳纳米管。 优选地，第一导体与第二导体相对定位。 空气粒子除尘器还包括适于向壳体单元施加电场的电场源。 此外，碳纳米管适于使壳体单元中的气体电离，其中电离气体对位于壳体单元中的气体微粒进行充电，并且其中第一导体适于捕集带电气体微粒。 空气粒子沉淀器还可以包括在碳纳米管上的金属层。

公开(公告)号：US07528494B2

公开(公告)日：2009-05-05

申请号：US11266456

申请日：2005-11-03

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/4763

CPC分类号： H01L29/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002

摘要： A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

摘要翻译： 制造三维集成电路芯片或晶片组件的过程，更具体地说，在将芯片定向成堆叠之前，将其布置在晶片上的处理。 还公开了三维集成电路的制造，其中芯片密度可以非常高并且在晶片仍然完整且通常为平面结构的情况下被处理。

公开(公告)号：US07504314B2

公开(公告)日：2009-03-17

申请号：US10907565

申请日：2005-04-06

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L29/93 ,  H01L21/76

CPC分类号： H01L21/76267 ,  H01L21/76243 ,  H01L21/76281 ,  H01L21/76283

摘要： The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.

摘要翻译： 本发明一般涉及一种用于制造氧注入半导体的方法，更具体地说，涉及一种用于将氧注入的硅绝缘（“SOI”）型半导体通过切割区域制造成器件尺寸的片之前的方法 SOI氧化工艺。 制造SOI的工艺顺序被修改，使得可以减少注入剂量并且相对较长并且可以缩短或消除高温退火工艺步骤。 如果在氧注入之后将晶片结构发送到焊盘形成以及掩模和蚀刻，则可以实现这种简化。 在蚀刻之后，可以执行退火或氧化工艺步骤以产生SOI晶片。

公开(公告)号：US07491631B2

公开(公告)日：2009-02-17

申请号：US11757660

申请日：2007-06-04

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/425

CPC分类号： H01L29/4983 ,  H01L29/4908 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78621 ,  Y10S977/742 ,  Y10S977/847

摘要： A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

摘要翻译： 一种制造结构并制造相关半导体晶体管和新型半导体晶体管结构的方法。 制造该结构的方法包括：提供具有顶表面的基底; 在所述基板的顶表面上形成岛，所述岛的顶表面平行于所述基底的顶表面，所述岛的侧壁在所述岛的顶表面和所述基底的顶表面之间延伸; 在岛的侧壁上形成多个碳纳米管; 并且进行离子注入，所述离子注入在所述岛状体和所述碳纳米管所掩盖的基板的区域中贯穿所述岛并阻止其侵入所述基板。

公开(公告)号：US20080286971A1

公开(公告)日：2008-11-20

申请号：US12186075

申请日：2008-08-05

申请人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/311

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/823828 ,  H01L21/823864

摘要： A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

摘要翻译： 用于形成亚光刻结构的侧壁图像转印工艺采用沉积在结构层上并被覆盖层覆盖的牺牲材料层。 牺牲材料层和覆盖层用常规抗蚀剂图案化并蚀刻以形成牺牲芯棒。 心轴的边缘在低温下在等离子体中被氧化或氮化，之后剥离材料层和覆盖层，留下亚光刻的侧壁。 侧壁用作硬掩模来蚀刻栅极导体层中的亚光刻栅极结构。