公开(公告)号：US6165897A

公开(公告)日：2000-12-26

申请号：US086823

申请日：1998-05-29

申请人： Syun-Ming Jang

发明人： Syun-Ming Jang

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612 ,  H01L21/7682

摘要： A method for forming a dielectric layer within a microelectronics fabrication. There is first provided a microelectronics substrate layer employed within a microelectronics fabrication. There is then formed upon the microelectronics substrate layer a patterned microelectronics layer. There is then formed conformally over the patterned microelectronics layer a conformal silicon oxide dielectric layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing silane as a silicon source material. The conformal silicon oxide dielectric layer comprises: (1) a first region formed over the upper surface of the patterned microelectronics layer; (2) a second region formed interposed between a series of patterns which comprises the patterned microelectronics layer and parallel with a series of sidewalls of the series of patterns which comprises the patterned microelectronics layer; and (3) a third region formed interposed between the series of patterns which comprises the patterned microelectronics layer but not parallel with the series of sidewalls of the series of patterns which comprises the patterned microelectronics layer. There is then treated with an oxygen containing plasma the conformal silicon oxide dielectric layer to enhance the rate of formation of a second silicon oxide dielectric layer upon the first region of the conformal silicon oxide dielectric layer with respect to at least the second region of the conformal silicon oxide dielectric layer. The second silicon oxide dielectric layer is formed employing an ozone assisted thermal chemical vapor deposition (CVD) method employing tetraethylorthosilicate (TEOS) as a silicon source material. Finally, there is then formed upon the oxygen containing plasma treated conformal silicon oxide dielectric layer the second silicon oxide dielectric layer, where the second silicon oxide dielectric layer defines, at least in part, a series of voids formed interposed between the series of patterns which comprises the patterned microelectronics layer.

公开(公告)号：US6090714A

公开(公告)日：2000-07-18

申请号：US177189

申请日：1998-10-23

申请人： Syun-Ming Jang ,  Chu-Yun Fu

发明人： Syun-Ming Jang ,  Chu-Yun Fu

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/76229 ,  H01L21/31055 ,  H01L21/31608

摘要： A method for forming a planarized trench fill layer within a trench within a substrate. There is first provided a substrate having a trench formed therein. There is then formed over the substrate and at least partially filling the trench a first trench fill layer formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. There is then formed upon the first trench fill layer a second trench fill layer formed employing a subatmospheric pressure thermal chemical vapor deposition (SACVD) method employing ozone as an oxidant source material and tetraethylorthosilicate (TEOS) as a silicon source material. Finally, there is then planarized by employing a chemical mechanical polish (CMP) planarizing method the second trench fill layer and the first trench fill layer to form a patterned planarized trench fill layer within the trench. When employing the method, the first trench fill layer is formed to a first thickness and the second trench fill layer is formed to a second thickness, where the first thickness and the second thickness are chosen such that there is attenuated erosion of the substrate when forming the patterned planarized trench fill layer within the trench while employing the chemical mechanical polish (CMP) planarizing method. The method is particularly useful for forming patterned planarized trench fill dielectric layers within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications.

摘要翻译： 一种用于在衬底内的沟槽内形成平坦化的沟槽填充层的方法。 首先提供其中形成有沟槽的衬底。 然后在衬底上形成并且至少部分地填充沟槽，使用高密度等离子体化学气相沉积（HDP-CVD）方法形成的第一沟槽填充层。 然后在第一沟槽填充层上形成第二沟槽填充层，该第二沟槽填充层采用使用臭氧作为氧化剂源材料和四乙基原硅酸盐（TEOS）作为硅源材料的低于大气压的热化学气相沉积（SACVD）方法。 最后，然后通过采用化学机械抛光（CMP）平面化方法平面化第二沟槽填充层和第一沟槽填充层，以在沟槽内形成图案化的平坦化沟槽填充层。 当采用该方法时，第一沟槽填充层被形成为第一厚度，并且第二沟槽填充层被形成为第二厚度，其中第一厚度和第二厚度被选择为使得当形成时基板受到衰减的侵蚀 在使用化学机械抛光（CMP）平面化方法的同时，在沟槽内形成图案化的平坦化沟槽填充层。 该方法对于在半导体集成电路微电子器件制造中使用的半导体衬底内的隔离沟槽内形成图案化的平坦化沟槽填充电介质层特别有用。

公开(公告)号：US6072237A

公开(公告)日：2000-06-06

申请号：US163382

申请日：1998-09-30

申请人： Syun-Ming Jang ,  Chen-Hua Douglas Yu

发明人： Syun-Ming Jang ,  Chen-Hua Douglas Yu

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01K23/04

CPC分类号： H01L23/53223 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

摘要： A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer. The thin silicon nitride layer is the top layer of an interlevel dielectric composite layer, used between metal interconnect levels.

摘要翻译： 已经开发了用于形成无边界，接触或通孔的方法，其中使用薄氮化硅层作为蚀刻停止件，以防止在无边界接触或通孔的打开期间侵入下面的层间电介质层 在叠层的层间电介质层中。 薄的氮化硅层是在金属互连层之间使用的层间介质复合层的顶层。

公开(公告)号：US6051496A

公开(公告)日：2000-04-18

申请号：US156052

申请日：1998-09-17

申请人： Syun-Ming Jang

发明人： Syun-Ming Jang

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： A method is disclosed for forming copper damascene interconnects without the attendant CMP (chemical-mechanical polishing) dishing problem that is encountered in the art. This is accomplished by first lining the inside walls of a dual damascene structure with a diffusion barrier layer, and then depositing copper metal into the damascene structure. Secondly, as a key aspect of the invention, and before removing the excess copper either by conventional etching techniques-which is difficult for copper- or by conventional CMP- which causes dishing in grooves or trenches- an etch stop layer is deposited covering the copper layer. Portions of the etch stop layer is next removed from the high regions of the underlying copper by a quick first CMP so that other portions of the etch stop layer over the wider trenches/groove remain low and unaffected. The high regions now exposed are etched while the low regions protected by the etch-stop layer still remain unaffected. When the copper etching reaches a level below the level of the low regions, a global CMP is performed so that all of the excess copper is removed and the level of the copper especially over the wider trench areas reaches within very close proximity of the level of the insulation layer surrounding the copper damascene- and without dishing.

摘要翻译： 公开了用于形成铜镶嵌互连的方法，而不伴随本领域遇到的伴随的CMP（化学 - 机械抛光）凹陷问题。 这通过首先用扩散阻挡层衬在双镶嵌结构的内壁上，然后将铜金属沉积到镶嵌结构中来实现。 其次，作为本发明的关键方面，并且在通过传统的蚀刻技术去除多余的铜之前，这对于铜或通过常规的CMP（其引起凹槽或沟槽中的凹陷）是困难的 - 沉积覆盖铜的蚀刻停止层 层。 接下来通过快速第一CMP从下面的铜的高区域去除蚀刻停止层的一部分，使得较宽沟槽/沟槽上的蚀刻停止层的其它部分保持低并且不受影响。 现在暴露的高区域被蚀刻，而由蚀刻停止层保护的低区域仍然不受影响。 当铜蚀刻达到低于低区域电平的水平时，执行全局CMP，以便除去所有过量的铜，并且特别是在更宽的沟槽区域上的铜的水平达到非常接近于 围绕铜镶嵌层的绝缘层 - 不带凹陷。

公开(公告)号：US6037018A

公开(公告)日：2000-03-14

申请号：US108866

申请日：1998-07-01

申请人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

发明人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Douglas Yu

IPC分类号： C23C16/40 ,  H01L21/762 ,  B05D3/06 ,  H01L21/76

CPC分类号： H01L21/76232 ,  C23C16/402

摘要： A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O.sub.3 -TEOS protective liner 40. The O.sub.3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O.sub.3 -TEOS layer has novel process temperature (400 to 560.degree. C.) and low pressure (40 to 80 torr) that allows the O.sub.3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O.sub.3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.

摘要翻译： 用HDPCVD氧化物50填充浅沟槽28的方法。本发明具有两个衬垫：（a）热氧化物衬垫36和（b）上覆的共形O3-TEOS保护衬垫40.O3-TEOS保护衬垫40防止 HDPCVD氧化物50从溅射破坏沟槽侧壁和掩模层24.O3-TEOS层具有新的工艺温度（400至560℃）和低压（40至80托），允许O 3 -TEOS层沉积 该方法开始于在衬底上形成衬垫氧化物层20和阻挡层24。 沟槽28通过衬垫氧化物层20和阻挡层24形成在衬底10中。热氧化物衬里36和保护性O 3 -TEOS衬里层40形成在沟槽28的壁上并且在阻挡层24上方 最后，在填充沟槽28的保护衬垫层40之上形成高密度等离子体化学气相沉积（HDPCVD）氧化物层50。

公开(公告)号：US6010948A

公开(公告)日：2000-01-04

申请号：US244879

申请日：1999-02-05

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： A process for creating BPSG filled, shallow trench isolation regions, in a semiconductor substrate, has been developed. The process features the use of a BPSG layer with about 4 to 4.5 weight percent B.sub.2 O.sub.3, and about 4 to 4.5 weight percent P.sub.2 O.sub.5, in silicon oxide. This BPSG composition, when subjected to a high temperature anneal procedure, results in softening, or reflowing, of the BPSG layer, eliminating seams or voids, in the BPSG layer, that may have been present after BPSG deposition. The removal rate of BPSG, is lower than the removal rate of silicon oxide layer, in buffered HF solutions, thus allowing several buffered HF procedures to be performed without recessing of BPSG in the shallow trench. In addition this composition of BPSG performs as a gettering material for mobile ions, thus contributing to yield and reliability improvements, when used at the isolation region for MOSFET devices.

摘要翻译： 已经开发了用于在半导体衬底中产生BPSG填充的浅沟槽隔离区的工艺。 该方法的特征在于在氧化硅中使用具有约4至4.5重量％的B 2 O 3和约4至4.5重量％的P 2 O 5的BPSG层。 当经过高温退火过程时，该BPSG组合物导致BPSG层的软化或回流，消除了在BPSG沉积后可能存在的BPSG层中的接缝或空隙。 BPSG的去除率低于缓冲HF溶液中氧化硅层的去除率，从而允许在浅沟槽中不进行BPSG的凹陷而执行几个缓冲的HF程序。 此外，BPSG的这种组合作为移动离子的吸气材料，当在MOSFET器件的隔离区域使用时，有助于提高产量和可靠性。

公开(公告)号：US5955787A

公开(公告)日：1999-09-21

申请号：US892220

申请日：1997-07-14

申请人： Chen-Hua Douglas Yu ,  Syun-Ming Jang

发明人： Chen-Hua Douglas Yu ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/441

CPC分类号： H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002

摘要： A defect free intermetal dielectric, IMD, and method of forming the defect free IMD are described. The IMD uses spacers formed by means of etchback of a layer of spin-on-glass, SOG. In order to use an oxide layer formed by means of plasma enhanced tetra-ethyl-ortho-silicate, PE-TEOS, as part of the IMD an oxide cap layer formed using plasma enhanced chemical vapor deposition, PE-CVD, is used to isolate the SOG spacers from the PE-TEOS formed oxide layer. By isolating the PE-TEOS formed oxide layer from the SOG spacers a reliable and defect free IMD is achieved.

摘要翻译： 描述了无缺陷的金属间电介质，IMD和形成无缺陷IMD的方法。 IMD使用通过回转一层旋涂玻璃（SOG）形成的间隔物。 为了使用通过等离子体增强的四乙基原硅酸盐形成的氧化物层，PE-TEOS作为IMD的一部分，使用等离子体增强化学气相沉积形成的氧化物覆盖层PE-CVD用于分离 来自PE-TEOS形成的氧化物层的SOG间隔物。 通过从SOG间隔隔离PE-TEOS形成的氧化物层，实现可靠且无缺陷的IMD。

公开(公告)号：US08962484B2

公开(公告)日：2015-02-24

申请号：US13328680

申请日：2011-12-16

申请人： Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai ,  Syun-Ming Jang

发明人： Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/32 ,  H01L21/311 ,  H01L21/033 ,  H01L21/308

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32

摘要： The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.

摘要翻译： 本公开提供了一种方法，包括提供半导体衬底并在半导体衬底上形成第一层和第二层。 图案化第一层以提供第一元件，第二元件和插入第一元件和第二元件的空间。 然后在第一层的第一和第二元件的侧壁上形成间隔元件。 随后，使用间隔元件和第一和第二元素作为掩模元件来蚀刻第二层。

公开(公告)号：US20130330906A1

公开(公告)日：2013-12-12

申请号：US13490635

申请日：2012-06-07

申请人： Weibo Yu ,  Ming-His Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Weibo Yu ,  Ming-His Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L29/66795

摘要： A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.

摘要翻译： 公开了制造半导体IC的方法。 该方法包括接收设备。 该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。 该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

公开(公告)号：US20130078809A1

公开(公告)日：2013-03-28

申请号：US13244337

申请日：2011-09-24

申请人： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L21/306

CPC分类号： H01L21/6708 ,  H01L21/31111

摘要： A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.

摘要翻译： 公开了在单晶片蚀刻装置中实现的单晶片蚀刻装置和各种方法。 在一个实施例中，在单晶片蚀刻装置中蚀刻氮化硅层包括：将磷酸加热到第一温度; 将硫酸加热至第二温度; 混合加热的磷酸和加热的硫酸; 将磷酸/硫酸混合物加热至第三温度; 并用加热的磷酸/硫酸混合物蚀刻氮化硅层。