公开(公告)号：US11856869B2

公开(公告)日：2023-12-26

申请号：US17809573

申请日：2022-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Feng Yin ,  Tai-Yen Peng ,  An-Shen Chang ,  Han-Ting Tsai ,  Qiang Fu ,  Chung-Te Lin

IPC: H10N50/80 ,  H01L21/768 ,  H01L23/522 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01L21/7684 ,  H01L23/5226 ,  H10N50/01

Abstract: The present disclosure provides a semiconductor structure, including a first metal line over a first region of the substrate, a first magnetic tunnel junction (MTJ) and a second MTJ over the first region of the substrate, and a top electrode extending over the first MTJ and the second MTJ, wherein the top electrode includes a protruding portion at a bottom surface of the top electrode.

公开(公告)号：US11856854B2

公开(公告)日：2023-12-26

申请号：US17465351

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Feng Yin ,  Min-Kun Dai ,  Chien-Hua Huang ,  Chung-Te Lin

IPC: H10N50/01 ,  G11C11/16 ,  H01L23/522 ,  H01L21/768 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/01 ,  G11C11/161 ,  H01L21/7684 ,  H01L21/76832 ,  H01L21/76879 ,  H01L23/5226 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

公开(公告)号：US20230395673A1

公开(公告)日：2023-12-07

申请号：US17832687

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Cheng Chu ,  Tzu-Hsiang Hsu ,  Pin-Cheng Hsu ,  Chung-Te Lin

IPC: H01L29/423 ,  H01L29/66

CPC classification number: H01L29/4236 ,  H01L29/42344 ,  H01L29/66704

Abstract: A transistor includes a gate electrode, a gate dielectric, a channel layer and a source line and bit line. The gate electrode includes a first gate material layer and a second gate material layer disposed on the first gate material layer, wherein a work function of the first gate material layer is lower than a work function of the second gate material layer. The gate dielectric is disposed on the gate electrode. The channel layer is disposed on the gate dielectric. The source line and bit line are disposed on and connected to the channel layer.

公开(公告)号：US20230380177A1

公开(公告)日：2023-11-23

申请号：US18363986

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L23/522

CPC classification number: H10B51/30 ,  H01L29/516 ,  H01L29/78391 ,  H01L29/40111 ,  H01L29/6684 ,  H01L23/5226

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.

公开(公告)号：US20230363173A1

公开(公告)日：2023-11-09

申请号：US17740331

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Han-Ting Tsai ,  Tsann Lin ,  Kuo-Chang Chiang ,  Min-Kun Dai ,  Chung-Te Lin

IPC: H01L27/1159

CPC classification number: H01L27/1159

Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.

公开(公告)号：US11810956B2

公开(公告)日：2023-11-07

申请号：US17570028

申请日：2022-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H10B51/00

CPC classification number: H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/00

Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated circuit (IC), including forming a first electrode layer having a first metal over a substrate, performing a first atomic layer deposition (ALD) pulse that exposes the first electrode layer to oxygen atoms, exposing the first electrode layer to a first temperature, the first temperature causing the first electrode layer to react with the oxygen atoms to form a seed structure over the first electrode layer, and performing a series of ALD pulses at a second temperature to form a ferroelectric structure over the seed structure. The second temperature is less than the first temperature and the ferroelectric structure is configured to store a data state.

公开(公告)号：US11800718B2

公开(公告)日：2023-10-24

申请号：US17375498

申请日：2021-07-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H10B43/35 ,  G11C5/06 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/35 ,  G11C5/063 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a via above a substrate, a dielectric layer over the via, a first source/drain feature above the dielectric layer, a first channel feature above the first source/drain feature, a second source/drain feature above the first channel feature, and a gate line laterally spaced apart from the first source/drain feature, the first channel feature and the second source/drain feature. The gate line passes through the dielectric layer and is on the via.

公开(公告)号：US11777010B2

公开(公告)日：2023-10-03

申请号：US17238925

申请日：2021-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/517 ,  H01L29/7831 ,  H01L29/78391

Abstract: A semiconductor structure includes a gate stack over a substrate and a blocking layer disposed between the gate stack and the substrate. The gate stack includes an upper electrode, a lower electrode, a ferroelectric layer disposed between the upper electrode and the lower electrode, and a first seed layer disposed between the ferroelectric layer and the lower electrode. The blocking layer includes doped hafnium oxide.

公开(公告)号：US20230262989A1

公开(公告)日：2023-08-17

申请号：US17673059

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1159 ,  H01L29/0665 ,  H01L29/6684 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a first electrode structure disposed in a substrate. A first ferroelectric structure is disposed on a first side of the first electrode structure. A channel structure is disposed on a first side of the first ferroelectric structure. The channel structure includes a plurality of individual channel structures and a plurality of insulator structures. The plurality of individual channel structures and the plurality of insulator structures are alternately stacked. A pair of source/drain (S/D) structures are disposed on the first side of the first ferroelectric structure. The pair of S/D structures extend vertically through the channel structure, and the first electrode structure is disposed laterally between the S/D structures of the pair of S/D structures.

公开(公告)号：US20230141313A1

公开(公告)日：2023-05-11

申请号：US17577037

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Huang ,  Gao-Ming Wu ,  Katherine H CHIANG ,  Chung-Te Lin

IPC: H01L29/417 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/41775 ,  H01L29/42364 ,  H01L29/4011

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes gate electrodes and first insulation patterns laterally disposed and alternately arranged on a substrate, a gate dielectric layer disposed on the gate electrodes and the first insulation patterns, at least one channel pattern disposed on the gate dielectric layer, source electrodes and drain electrodes laterally disposed and alternately arranged on the channel pattern, and second insulation patterns disposed on the channel pattern between the source and drain electrodes. Besides, from a top view, each of the drain electrodes is overlapped with one of the first insulation patterns.