公开(公告)号：US20240371869A1

公开(公告)日：2024-11-07

申请号：US18775025

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yu-Hsien Lin ,  Ming-Ching Chang ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Yi-Chun Chen

IPC: H01L27/088 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

公开(公告)号：US20240290867A1

公开(公告)日：2024-08-29

申请号：US18655832

申请日：2024-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42368 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.

公开(公告)号：US12009406B2

公开(公告)日：2024-06-11

申请号：US17345188

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42368 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.

公开(公告)号：US20240113113A1

公开(公告)日：2024-04-04

申请号：US18526290

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H01L27/088 ,  H01L21/283 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/283 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L21/02068 ,  H01L29/6656

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US11915980B2

公开(公告)日：2024-02-27

申请号：US18064726

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Yi-Hsuan Hsiao ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

公开(公告)号：US11908920B2

公开(公告)日：2024-02-20

申请号：US17722787

申请日：2022-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/30621 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7856 ,  H01L2029/7858

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

公开(公告)号：US11810909B2

公开(公告)日：2023-11-07

申请号：US17218284

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ming-Ching Chang

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/027 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L27/0207 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L21/0276 ,  H01L21/28556 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636

Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.

公开(公告)号：US11721588B2

公开(公告)日：2023-08-08

申请号：US17341163

申请日：2021-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chang Hung ,  Shu-Yuan Ku ,  I-Wei Yang ,  Yi-Hsuan Hsiao ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823481

Abstract: The first and second fins extend upwardly from a semiconductor substrate. The shallow trench isolation structure laterally surrounds lower portions of the first and second fins. The first gate structure extends across an upper portion of the first fin. The second gate structure extends across an upper portion of the second fin. The first source/drain epitaxial structures are on the first fin and on opposite sides of the first gate structure. The second source/drain epitaxial structures are on the second fin and on opposite sides of the second gate structure. The separation plug interposes the first and second gate structures and extends along a lengthwise direction of the first fin. The isolation material cups an underside of a portion of the separation plug between one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures.

公开(公告)号：US11616061B2

公开(公告)日：2023-03-28

申请号：US16195258

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Chun-Liang Lai ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3105

Abstract: A method includes providing a structure having a substrate, semiconductor fins, and an isolation structure between adjacent semiconductor fins; forming a first gate structure engaging the semiconductor fins; depositing an inter-layer dielectric layer over the semiconductor fins and the first gate structure; removing the first gate structure, resulting in a first trench; depositing a second gate structure into the first trench, wherein the second gate structure includes a dielectric layer and a conductive layer; forming one or more mask layers over the second gate structure; patterning the one or more mask layers to have an opening exposing a portion of the second gate structure between two adjacent semiconductor fins; and etching the second gate structure through the opening to produce a second trench having tapered sidewalls, wherein the second trench is wider at top than at bottom.

公开(公告)号：US20220359207A1

公开(公告)日：2022-11-10

申请号：US17869057

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.