公开(公告)号：US20210242217A1

公开(公告)日：2021-08-05

申请号：US17234201

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Chia-Ta Yu ,  Cheng-Yu Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

公开(公告)号：US20210134985A1

公开(公告)日：2021-05-06

申请号：US17121007

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/225 ,  H01L29/165

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US20200051830A1

公开(公告)日：2020-02-13

申请号：US16656393

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chunhung Chen ,  Sheng-Chen Wang ,  Chin Wei Chuang

IPC: H01L21/321 ,  G01N23/20 ,  H01L21/66 ,  G06F11/07

Abstract: A planarization process is performed to a wafer. In various embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. A byproduct generated by the planarization process is collected and analyzed. Based on the analysis, one or more process controls are performed for the planarization process. In some embodiments, the process controls include but are not limited to process endpoint detection or halting the planarization process based on detecting an error associated with the planarization process.

公开(公告)号：US10529803B2

公开(公告)日：2020-01-07

申请号：US15814129

申请日：2017-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Wei-Yuan Lu ,  Chien-I Kuo ,  Li-Li Su ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  H01L29/267 ,  H01L29/165

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).

公开(公告)号：US09449882B1

公开(公告)日：2016-09-20

申请号：US14927190

申请日：2015-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Chen Wang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chia-Ta Yu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and second semiconductor layers. A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure. An insulating layer is formed so that the fin structure is embedded in the insulating layer. A part of the upper portion is removed so that an opening is formed in the insulating layer. A third semiconductor layer is formed in the opening on the remaining layer of the second semiconductor layer. The insulating layer is recessed so that a part of the third semiconductor layer is exposed from the insulating layer, and a gate structure is formed.

Abstract translation: 在制造半导体器件时，形成第一和第二半导体层的叠层。 通过图案化第一和第二半导体层来形成翅片结构。 覆盖层形成在翅片结构的底部，以覆盖翅片结构的底部的侧壁和翅片结构的上部的侧壁的底部。 形成绝缘层，使得翅片结构嵌入绝缘层中。 去除上部的一部分，使得在绝缘层中形成开口。 在第二半导体层的剩余层上的开口中形成第三半导体层。 绝缘层凹陷，使得第三半导体层的一部分从绝缘层露出，形成栅极结构。

公开(公告)号：US12249640B2

公开(公告)日：2025-03-11

申请号：US18524417

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L29/165 ,  H01L29/66

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US20240381656A1

公开(公告)日：2024-11-14

申请号：US18783024

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H10B51/20 ,  G11C11/22 ,  G11C11/56 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US12128522B2

公开(公告)日：2024-10-29

申请号：US17871259

申请日：2022-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Bin Hsu ,  Ren-Guei Lin ,  Feng-Inn Wu ,  Sheng-Chen Wang ,  Jung-Yu Li

IPC: B24B37/26 ,  B24B49/00 ,  B24B49/10 ,  B24B49/16 ,  B24B57/02

CPC classification number: B24B37/26 ,  B24B49/00 ,  B24B49/10 ,  B24B49/16 ,  B24B57/02

Abstract: A method includes supplying slurry onto a polishing pad; holding a wafer against the polishing pad with a piezoelectric layer interposed vertically between a pressure unit and the wafer; exerting a force on the piezoelectric layer using the pressure unit to make the piezoelectric layer directly press the wafer; generating, using the piezoelectric layer, a first voltage corresponding to a first portion of the wafer and a second voltage corresponding to a second portion of the wafer; tuning the force exerted on the piezoelectric layer according to the first voltage and the second voltage; and polishing, using the polishing pad, the wafer.

公开(公告)号：US20240331754A1

公开(公告)日：2024-10-03

申请号：US18742089

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Sheng-Chen Wang ,  Yu-Ming Lin

IPC: G11C11/22 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

CPC classification number: G11C11/2257 ,  G11C11/223 ,  G11C11/2255 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

公开(公告)号：US12087621B2

公开(公告)日：2024-09-10

申请号：US18178773

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chia-Ta Yu ,  Han-Jong Chia

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532 ,  H01L29/24 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L21/7682 ,  H01L21/02565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/24 ,  H10B51/20 ,  H10B51/30

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.