公开(公告)号：US09673204B2

公开(公告)日：2017-06-06

申请号：US14584735

申请日：2014-12-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Ming Wu ,  Tsung-Hsueh Yang ,  Chung-Chiang Min ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L27/11521 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11519 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/11519 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure also includes a first isolation structure partially embedded in the substrate. The first isolation structure has a first upper surface with a first recess. The semiconductor device structure further includes a second isolation structure partially embedded in the substrate. In addition, the semiconductor device structure includes a first gate over the substrate and between the first isolation structure and the second isolation structure. The first gate extends onto the first upper surface to cover the first recess. The semiconductor device structure includes a second gate over the first gate.

公开(公告)号：US09614145B2

公开(公告)日：2017-04-04

申请号：US14918671

申请日：2015-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L29/82 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

公开(公告)号：US20160365350A1

公开(公告)日：2016-12-15

申请号：US15245539

申请日：2016-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/423 ,  H01L21/3213

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.

Abstract translation: 提供了一种制造嵌入式闪存设备的方法。 一对栅极叠层形成在半导体衬底上间隔开，并且在浮动栅极上包括浮动栅极和控制栅极。 在栅极堆叠和半导体衬底上形成公共栅极层，并且栅极堆叠的衬里侧壁。 在公共栅极层中执行第一蚀刻，以将公共栅极层的上表面分别凹入栅极堆叠的下表面，并在栅极堆叠之间形成擦除栅极。 硬掩模分别形成在擦除栅极，公共栅极层的字线区域和公共栅极层的逻辑门极区域上。 第二蚀刻被执行到具有硬掩模的公共栅层中，以同时形成字线和逻辑门。

公开(公告)号：US09496276B2

公开(公告)日：2016-11-15

申请号：US14092912

申请日：2013-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11573

Abstract: A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the substrate. The split gate memory device is located on the substrate and comprises a memory gate and a select gate. The memory gate and the select gate are adjacent to and electrically isolated with each other. A top of the select gate is higher than a top of the memory gate.

Abstract translation: 半导体器件包括衬底，至少一个逻辑器件和分离栅极存储器件。 至少一个逻辑器件位于衬底上。 分离栅极存储器件位于衬底上并且包括存储器栅极和选择栅极。 存储器栅极和选择栅极彼此相邻并且电隔离。 选择栅极的顶部高于存储器栅极的顶部。

公开(公告)号：US09484352B2

公开(公告)日：2016-11-01

申请号：US14573208

申请日：2014-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.

Abstract translation: 提供了一种嵌入式闪存设备。 栅极堆叠包括布置在浮动栅极上的控制栅极。 擦除栅极邻近栅堆叠的第一侧布置。 字线布置成与栅堆叠的与第一侧相对的第二侧相邻。 字线包括字线凸出部，该字线突出部相对于字线的顶表面减小高度，并且与字线堆叠在字线的相反侧。 多晶硅逻辑门具有大致均匀的字线凸缘的顶表面。 ILD层布置在栅极堆叠，擦除栅极，多晶硅逻辑门和字线之上。 一个触点延伸穿过ILD层。 还提供了一种制造嵌入式闪存设备的方法。

公开(公告)号：US20160247812A1

公开(公告)日：2016-08-25

申请号：US15143811

申请日：2016-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。 第一和第二源极/漏极区域之间形成沟道区域。 半导体结构还包括选择栅极和在沟道区域上的第一和第二源极/漏极区域间隔开的存储栅极。 选择栅极延伸在沟道区上方并且终止于具有沿着沿着选择栅极的长度延伸的轴线的不对称的顶表面的线端，并且平分选择栅极的宽度。 更重要的是，半导体结构包括布置在存储器栅极和选择栅极的相邻侧壁之间并且布置在存储器栅极下方的电荷捕获电介质。 还提供了制造半导体结构的方法。

公开(公告)号：US09425044B2

公开(公告)日：2016-08-23

申请号：US14461565

申请日：2014-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L21/02601 ,  H01L21/02532 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

Abstract: Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact.

Abstract translation: 一些实施例涉及包括设置在控制栅极和选择栅极之间的电荷捕获层的存储器件。 封盖结构设置在控制栅极的上表面上，并且复合间隔物设置在控制栅极的面向源的侧壁表面上。 封盖结构和复合间隔物在用于与存储器件的接触形成的一个以上蚀刻工艺期间防止对控制栅极的损坏。 为了进一步限制或防止选择栅极侧壁蚀刻，一些实施例提供沿着选择栅极的面向排水的侧壁表面设置的附加衬垫氧化物层。 衬里氧化物层被配置为蚀刻停止层，以防止在一个或多个蚀刻工艺期间蚀刻选择栅极。 结果，一个或多个蚀刻工艺离开控制栅极并基本上完整地选择栅极。

公开(公告)号：US09397228B2

公开(公告)日：2016-07-19

申请号：US14560353

申请日：2014-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chang-Ming Wu ,  Wei-Hang Huang ,  Shih-Chang Liu

IPC: H01L21/3205 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L29/66825 ,  H01L27/11531 ,  H01L29/42328

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The semiconductor device structure includes a second gate stack over the semiconductor substrate. The semiconductor device structure includes an erase gate between the first gate stack and the second gate stack. The erase gate has a recess recessed toward the semiconductor substrate. The semiconductor device structure includes a first word line adjacent to the first gate stack. The semiconductor device structure includes a second word line adjacent to the second gate stack.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括半导体衬底。 半导体器件结构包括半导体衬底上的第一栅极堆叠。 半导体器件结构包括半导体衬底上的第二栅极堆叠。 半导体器件结构包括在第一栅极堆叠和第二栅极堆叠之间的擦除栅极。 擦除栅极具有朝向半导体衬底凹陷的凹陷。 半导体器件结构包括与第一栅极堆叠相邻的第一字线。 半导体器件结构包括与第二栅极堆叠相邻的第二字线。

公开(公告)号：US20160181268A1

公开(公告)日：2016-06-23

申请号：US14580454

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Fang-Lan Chu

IPC: H01L27/115

CPC classification number: H01L27/11573 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

Abstract translation: 本公开涉及用于减少集成电路中的CMP凹陷的结构和方法。 在一些实施例中，该结构具有具有嵌入的存储区域和外围区域的半导体衬底。 在存储区域和外围区域之间形成一个或多个虚拟结构。 在嵌入的存储区域和外围区域之间的虚拟结构的放置使得其之间的沉积层的表面在抛光之后变得更平坦，而不会产生凹陷效应。 减少的凹陷减少金属残留物的形成，从而导致金属残留物导致的电流泄漏和短路。 此外，较少的凹陷将减少有源器件的多晶硅损耗。 在一些实施例中，虚拟结构之一形成有成角度的侧壁，其消除了对边界切割蚀刻工艺的需要。

公开(公告)号：US20160181266A1

公开(公告)日：2016-06-23

申请号：US14573208

申请日：2014-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.

Abstract translation: 提供了一种嵌入式闪存设备。 栅极堆叠包括布置在浮动栅极上的控制栅极。 擦除栅极邻近栅堆叠的第一侧布置。 字线布置成与栅堆叠的与第一侧相对的第二侧相邻。 字线包括字线凸出部，该字线突出部相对于字线的顶表面减小高度，并且与字线堆叠在字线的相反侧。 多晶硅逻辑门具有大致均匀的字线凸缘的顶表面。 ILD层布置在栅极堆叠，擦除栅极，多晶硅逻辑门和字线之上。 一个触点延伸穿过ILD层。 还提供了一种制造嵌入式闪存设备的方法。