Magnetoresistive element and method for producing the same, as well as magnetic head, magnetic memory and magnetic recording device using the same
    61.
    发明授权
    Magnetoresistive element and method for producing the same, as well as magnetic head, magnetic memory and magnetic recording device using the same 失效
    磁阻元件及其制造方法以及使用该磁阻元件的磁头,磁存储器和磁记录装置

    公开(公告)号:US06943041B2

    公开(公告)日:2005-09-13

    申请号:US10719412

    申请日:2003-11-21

    摘要: The present invention provides a method for producing a magnetoresistive element including a tunnel insulating layer, and a first magnetic layer and a second magnetic layer that are laminated so as to sandwich the tunnel insulating layer, wherein a resistance value varies depending on a relative angle between magnetization directions of the first magnetic layer and the second magnetic layer. The method includes the steps of: (i) laminating a first magnetic layer, a third magnetic layer and an Al layer successively on a substrate; (ii) forming a tunnel insulating layer containing at least one compound selected from the group consisting of an oxide, nitride and oxynitride of Al by performing at least one reaction selected from the group consisting of oxidation, nitriding and oxynitriding of the Al layer; and (iii) forming a laminate including the first magnetic layer, the tunnel insulating layer and a second magnetic layer by laminating the second magnetic layer in such a manner that the tunnel insulating layer is sandwiched by the first magnetic layer and the second magnetic layer. The third magnetic layer has at least one crystal structure selected from the group consisting of a face-centered cubic crystal structure and a face-centered tetragonal crystal structure and is (111) oriented parallel to a film plane of the third magnetic layer. According to this production method, it is possible to produce a magnetoresistive element with excellent properties and thermal stability.

    摘要翻译: 本发明提供了一种制造磁阻元件的方法,该磁阻元件包括隧道绝缘层,以及第一磁性层和第二磁性层,其被层压以夹住隧道绝缘层,其中电阻值根据相对角度而变化 第一磁性层和第二磁性层的磁化方向。 该方法包括以下步骤:(i)在衬底上依次层叠第一磁性层,第三磁性层和Al层; (ii)通过进行选自Al层的氧化,氮化和氮氧化的至少一种反应,形成包含至少一种选自Al的氧化物,氮化物和氮氧化物的化合物的隧道绝缘层; 以及(iii)通过层叠所述第二磁性层来形成包括所述第一磁性层,所述隧道绝缘层和第二磁性层的层压体,使得所述隧道绝缘层被所述第一磁性层和所述第二磁性层夹在中间。 第三磁性层具有至少一种选自面心立方晶体结构和面心四边形晶体结构的晶体结构,并且(111)取向为平行于第三磁性层的膜平面。 根据该制造方法,可以制造出具有优异性能和热稳定性的磁阻元件。

    Semiconductor integrated circuit and fabrication method thereof
    63.
    发明申请
    Semiconductor integrated circuit and fabrication method thereof 有权
    半导体集成电路及其制造方法

    公开(公告)号:US20050040436A1

    公开(公告)日:2005-02-24

    申请号:US10866093

    申请日:2004-06-14

    IPC分类号: H01L21/8238 H01L27/10

    CPC分类号: H01L21/823807

    摘要: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

    摘要翻译: 根据本发明的半导体集成电路制造方法包括:通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤,由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

    CMOS and HCMOS semiconductor integrated circuit
    66.
    发明授权
    CMOS and HCMOS semiconductor integrated circuit 失效
    CMOS和HCMOS半导体集成电路

    公开(公告)号:US07564073B2

    公开(公告)日:2009-07-21

    申请号:US11294566

    申请日:2005-12-06

    IPC分类号: H01L27/04

    CPC分类号: H01L21/823807

    摘要: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

    摘要翻译: 根据本发明的半导体集成电路制造方法包括:通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤,由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

    Lid unit for thin plate supporting container
    68.
    发明申请
    Lid unit for thin plate supporting container 审中-公开
    薄板支撑容器盖单元

    公开(公告)号:US20050218034A1

    公开(公告)日:2005-10-06

    申请号:US11087078

    申请日:2005-03-23

    申请人: Yoshio Kawashima

    发明人: Yoshio Kawashima

    CPC分类号: H01L21/67369

    摘要: A lid unit seals a container main body of a thin-plate supporting container which is conveyed while plural 300 mm-diameter semiconductor wafers are stored in the container. In a wafer retainer which supports the wafers stored in the container main body, the maximum amount of displacement is set in a range of 1.5 to 2.5 mm (ranges from 1/200 to 1/120 of the semiconductor wafer diameter), and proportionality is held between the amount of displacement and external force when the maximum amount of displacement ranges from 1.5 to 2.5 mm. In the states in which the wafer retainer is fitted in the container main body and force is not applied, the wafer retainer is arranged at a position in which the wafer retainer is not in contact with the semiconductor wafers stored in the container main body or at a position in which the wafer retainer is in slight contact with the semiconductor wafers. Therefore, the lid unit can be attached and detached without fixing the container main body, so that vibration-resistant performance and shock-resistant performance are improved by preventing spring resistance force from rapidly increasing, and automatization of the attachment and detachment of the lid unit is easy to realize.

    摘要翻译: 盖单元将多个300mm直径的半导体晶片存储在容器中的薄板支撑容器的容器主体密封,该容器主体被输送。 在支撑存储在容器主体中的晶片的晶片保持器中,最大位移量设定在1.5〜2.5mm(半导体晶片直径的1/200〜1/120的范围)的范围内,比例为 当最大位移量范围为1.5至2.5mm时,位移量与外力之间保持不变。 在晶片保持器装配在容器主体中并且不施加力的状态下,晶片保持器布置在晶片保持器不与存储在容器主体中的半导体晶片接触的位置处或者 晶片保持器与半导体晶片轻微接触的位置。 因此,可以在不固定容器主体的情况下将盖单元安装和拆卸,从而通过防止弹簧阻力急剧增加来提高防振性能和抗冲击性能,并且使盖单元的安装和拆卸自动化 很容易实现。