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公开(公告)号：US07833873B2
公开(公告)日：2010-11-16
申请号：US12174683
申请日：2008-07-17
IPC分类号： H01L21/76
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.
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62.发明授权Apparatus for implementing enhanced hand shake protocol in microelectronic communication systems 失效用于在微电子通信系统中实现增强的手抖动协议的装置公开(公告)号：US07809340B2
公开(公告)日：2010-10-05
申请号：US12127159
申请日：2008-05-27
IPC分类号： H04B1/04
CPC分类号： H04B1/38
摘要： An apparatus is provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common 10 mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the 15 transmitter terminates communications, drops the common mode level with the idle input being activated.
摘要翻译： 提供了一种用于实现用于微电子通信系统的增强的手抖动协议的装置。 发射机和接收机通过传输链路耦合在一起。 发射机接收空闲输入。 当发射机不发送数据并且发射机向接收单元施加第一公共10模式电平时，空闲输入被激活。 当发射机准备好传输数据并且发射机将共模电平提升到接收单元时，空闲输入被去激活。 响应于接收机检测共模水平上移，接收器接收发送的数据信号。 在发送所需数据之后，15个发射机终止通信，在空闲输入被激活时降低共模电平。
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63.发明授权公开(公告)号：US07611931B2
公开(公告)日：2009-11-03
申请号：US11928135
申请日：2007-10-30
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/0218 , H01L27/10841 , H01L27/10864 , H01L27/10891
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.
摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触 晶圆。 半导体本体包括用于垂直存储单元之一的存取装置的通道区域。 延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。 可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。
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公开(公告)号：US20080274597A1
公开(公告)日：2008-11-06
申请号：US12174683
申请日：2008-07-17
IPC分类号： H01L21/336
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.
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65.发明申请METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS 有权使用这种方法形成多孔层和半导体结构形成绝缘体绝缘体半导体结构的方法公开(公告)号：US20080211054A1
公开(公告)日：2008-09-04
申请号：US12120455
申请日：2008-05-14
IPC分类号： H01L29/16
CPC分类号： H01L21/76251 , H01L21/76245 , Y10S438/933
摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
摘要翻译： 一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。 在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。 多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。 或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。 在转移之后，绝缘层被埋在后面的衬底和含锗层之间。
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66.发明申请Hybrid Field Effect Transistor and Bipolar Junction Transistor Structures and Methods for Fabricating Such Structures 审中-公开混合场效应晶体管和双极结晶体管结构和制造这种结构的方法公开(公告)号：US20080001234A1
公开(公告)日：2008-01-03
申请号：US11427962
申请日：2006-06-30
IPC分类号： H01L29/76
CPC分类号： H01L29/732 , H01L21/8249 , H01L21/84 , H01L27/0623 , H01L27/12 , H01L29/66265 , H01L29/785
摘要： Semiconductor device structures that integrate field effect transistors and bipolar junction transistors on a single substrate, such as a semiconductor-on-insulator substrate, and methods for fabricating such hybrid semiconductor device structures. The field effect and bipolar junction transistors are fabricated using adjacent electrically-isolated semiconductor bodies. During fabrication of the device structures, certain fabrication stages strategically rely on block masks for process isolation. Other fabrication stages are shared during the fabrication process for seamless integration that reduces process complexity.
摘要翻译： 在诸如绝缘体上半导体衬底的单个衬底上集成场效应晶体管和双极结型晶体管的半导体器件结构以及用于制造这种混合半导体器件结构的方法。 使用相邻的电隔离半导体器件制造场效应和双极结晶体管。 在器件结构的制造过程中，某些制造阶段有策略地依靠块掩模来进行过程隔离。 其他制造阶段在无缝集成的制造过程中共享，从而降低了工艺复杂性。
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公开(公告)号：US20080001187A1
公开(公告)日：2008-01-03
申请号：US11427486
申请日：2006-06-29
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
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68.发明授权High performance logic and high density embedded dram with borderless contact and antispacer 失效高性能逻辑和高密度嵌入式电脑，无边界接触和对抗公开(公告)号：US06709926B2
公开(公告)日：2004-03-23
申请号：US10160540
申请日：2002-05-31
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译： 集成电路包括具有以最小光刻特征尺寸分隔的阵列晶体管的存储单元，以及由扩散阻挡层封装的非硅化金属位线，而高性能逻辑晶体管可以形成在同一芯片上，而不会损害性能，包括有效沟道硅化触点低 源极/漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅极电介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。 该结构通过易平坦化的材料实现，并且使用平坦化为不同材料的结构的高度的类似掩模来去耦合逻辑晶体管中的衬底和栅极注入。
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69.发明授权Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS 失效在沟槽有限的埋沟p-MOSFET中减少异常窄通道效应的方法
公开(公告)号：US5858825A
公开(公告)日：1999-01-12
申请号：US893053
申请日：1997-07-14
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/092 , H01L29/06 , H01L29/10 , H01L29/78 , H01L21/8238
CPC分类号： H01L27/10873 , H01L21/823412 , H01L27/0921 , H01L29/0642 , H01L29/1033 , H01L29/1095 , H01L29/7838
摘要： Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850.degree. C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850.degree. C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850.degree. C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850.degree. C. gate oxidation step may follow the RTO gate oxidation step.
摘要翻译： 制造用于动态随机存取存储器（DRAM）技术的沟槽边界掩埋沟道p型金属氧化物半导体场效应晶体管（p-MOSFET）的方法，用于显着降低器件的异常埋沟p-MOSFET灵敏度 宽度。 在一个实施方案中，该方法包括在深磷n阱注入步骤之后，以及在硼掩埋沟道注入和850℃栅极氧化步骤之前使用惰性气体引发低温退火步骤。 或者，退火步骤可以在硼掩埋沟道植入之后和在850℃的栅极氧化步骤之前进行。 在另一个实施方案中，在深磷正构阱和硼掩埋沟道注入步骤之后，快速热氧化（RTO）步骤代替850℃的栅极氧化步骤。 或者，850℃的栅极氧化步骤可以在RTO栅极氧化步骤之后。
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70.发明授权Lateral field emission devices for display elements and methods of fabrication 失效用于显示元件的横向场致发射器件和制造方法
公开(公告)号：US5751097A
公开(公告)日：1998-05-12
申请号：US789175
申请日：1997-01-24
CPC分类号： H01J3/022 , H01J2201/30423
摘要： Lateral field emission devices ("FEDs") for display elements and methods of fabrication are set forth. The FED includes a thin-film emitter oriented parallel to, and disposed above, a substrate. The FED further includes a columnar shaped anode having a first lateral surface. A phosphor layer is disposed adjacent to the first lateral surface. Specifically, the anode is oriented such that the lateral surface and adjacent phosphor layer are perpendicular to the substrate. The emitter has a tip which is spaced less than the mean free distance of an electron in air from the phosphor layer. Operationally, when a voltage potential is applied between said anode and said emitter, electrons are emitted from the tip of the emitter into the phosphor layer causing the phosphor layer to emit electromagnetic energy. Further specific details of the field emission device, fabrication method, method of operation, and associated display are set forth.
摘要翻译： 阐述了用于显示元件和制造方法的侧面场致发射器件（“FED”）。 FED包括平行于并设置在基板上方的薄膜发射极。 FED还包括具有第一侧表面的柱状阳极。 磷光体层邻近第一侧面设置。 具体地，阳极被定向成使得侧表面和相邻磷光体层垂直于衬底。 发射器具有一个尖端，该尖端的距离小于空气中的电子与荧光体层的平均自由距离。 在工作上，当在所述阳极和所述发射极之间施加电压电位时，电子从发射极的尖端发射到荧光体层中，从而使荧光层发射电磁能。 阐述了场致发射装置，制造方法，操作方法和相关显示器的进一步具体细节。
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