公开(公告)号：US08131989B2

公开(公告)日：2012-03-06

申请号：US12081204

申请日：2008-04-11

Applicant: Stephen Anthony Fischer ,  Varghese George ,  Sanjeev Jahagirdar ,  Stephen H. Gunther

Inventor： Stephen Anthony Fischer ,  Varghese George ,  Sanjeev Jahagirdar ,  Stephen H. Gunther

IPC: G06F1/24

CPC classification number: G06F21/57 ,  G06F1/324 ,  G06F1/3296 ,  G06F21/575 ,  G06F21/70 ,  G06F21/81 ,  G06F2221/2101 ,  Y02D10/126

Abstract: A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.

Abstract translation: 提供了一种用于建立安全处理器工作点的系统和方法。 一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。 一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。

公开(公告)号：US08065555B2

公开(公告)日：2011-11-22

申请号：US11363150

申请日：2006-02-28

Applicant: Subramaniam Maiyuran ,  Varghese George ,  Vladimir Pentkovski ,  Sanjib Sarkar ,  Marina Sherman

Inventor： Subramaniam Maiyuran ,  Varghese George ,  Vladimir Pentkovski ,  Sanjib Sarkar ,  Marina Sherman

IPC: G06F11/00

CPC classification number: G06F11/1064

Abstract: A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.

Abstract translation: 方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于 第一组数据。 方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。

公开(公告)号：US20100146311A1

公开(公告)日：2010-06-10

申请号：US12706631

申请日：2010-02-16

Applicant: Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/00

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。

公开(公告)号：US07299370B2

公开(公告)日：2007-11-20

申请号：US10459011

申请日：2003-06-10

Applicant: Varghese George ,  Mark A. Newman ,  Sanjeev Jahagirdar ,  Inder M. Sodhi ,  Tanjeer R. Khondker ,  Mathew B. Nazareth ,  John B. Conrad

Inventor： Varghese George ,  Mark A. Newman ,  Sanjeev Jahagirdar ,  Inder M. Sodhi ,  Tanjeer R. Khondker ,  Mathew B. Nazareth ,  John B. Conrad

IPC: G01R23/02

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.

Abstract translation: 公开了一种自动转移到处理器的增强型低功率状态的方法和装置。 在一个实施例中，处理器核心时钟分配网格的全部或一部分可以在这些增强的低功率状态中掉电。 在一个实施例中，处理器可以以降低的电源电压工作，并且在这些增强的低功率状态期间以降低的频率工作。 在一个实施例中，可以保留时钟分配网格的一部分以便以降低的频率来支持窥探操作。

公开(公告)号：US20070226589A1

公开(公告)日：2007-09-27

申请号：US11363150

申请日：2006-02-28

Applicant: Subramaniam Maiyuran ,  Varghese George ,  Vladimir Pentkovski ,  Sanjib Sarkar ,  Marina Sherman

Inventor： Subramaniam Maiyuran ,  Varghese George ,  Vladimir Pentkovski ,  Sanjib Sarkar ,  Marina Sherman

IPC: G11C29/00

CPC classification number: G06F11/1064

Abstract: A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.

Abstract translation: 方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于 第一组数据。 方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。

公开(公告)号：US20070005900A1

公开(公告)日：2007-01-04

申请号：US11471773

申请日：2006-06-20

Applicant: John Horrigan ,  Namasivayam Thangavelu ,  Varghese George ,  Brian Holscher

Inventor： John Horrigan ,  Namasivayam Thangavelu ,  Varghese George ,  Brian Holscher

IPC: G06F13/28

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0897

Abstract: Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.

Abstract translation: 缓存的一部分被分阶段刷新。 本发明的示例性冲洗包括冲洗第一部分，执行除冲洗以外的操作，然后冲洗高速缓存的第二部分。 冲洗后第一部分可能被禁用。 高速缓存可以在功能上划分为冲洗之前的部分，或者部分可以部分地由中止信号确定。 操作可以访问缓存或存储器。 这些操作可能涉及直接存储器访问或中断服务。

公开(公告)号：US20060161373A1

公开(公告)日：2006-07-20

申请号：US11024679

申请日：2004-12-30

Applicant: Kedar Mangrulkar ,  Sanjeev Jahagirdar ,  Varghese George ,  Venkatesh Prasanna ,  Inder Sodhi

Inventor： Kedar Mangrulkar ,  Sanjeev Jahagirdar ,  Varghese George ,  Venkatesh Prasanna ,  Inder Sodhi

IPC: G01K1/00 ,  G01K3/00

CPC classification number: G01K7/42 ,  G01K3/005

Abstract: A device and method for continually monitoring multiple thermal sensors located at hotspots across a processor. The sensors are connected to a sensor cycling and selection block located at a periphery of the die. The output from the sensor selection block is converted into a digital temperature code. Based on the digital temperature code, thermal events trigger various thermal controls. The thermal event triggers may be software-programmable, providing flexible temperature management.

Abstract translation: 一种用于连续监测位于热点处的多个热传感器的装置和方法。 传感器连接到位于模具周边的传感器循环和选择块。 传感器选择块的输出转换为数字温度代码。 基于数字温度代码，热事件触发各种热控制。 热事件触发器可以是软件可编程的，提供灵活的温度管理。

公开(公告)号：US07061274B2

公开(公告)日：2006-06-13

申请号：US10671416

申请日：2003-09-24

Applicant: Varghese George

Inventor： Varghese George

IPC: H03K19/094

CPC classification number: H03K19/01759

Abstract: The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes. The method includes applying a configuration signal on one of the first and second signal nodes and configuring the buffer responsive to the applied configuration signal.

公开(公告)号：US20060069903A1

公开(公告)日：2006-03-30

申请号：US10953771

申请日：2004-09-30

Applicant: Stephen Fischer ,  Varghese George ,  Sanjeev Jahagirdar ,  Stephen Gunther

Inventor： Stephen Fischer ,  Varghese George ,  Sanjeev Jahagirdar ,  Stephen Gunther

IPC: G06F9/00

CPC classification number: G06F21/57 ,  G06F1/324 ,  G06F1/3296 ,  G06F21/575 ,  G06F21/70 ,  G06F21/81 ,  G06F2221/2101 ,  Y02D10/126

Abstract: A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.

Abstract translation: 提供了一种用于建立安全处理器工作点的系统和方法。 一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。 一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。

公开(公告)号：US06988211B2

公开(公告)日：2006-01-17

申请号：US09751528

申请日：2000-12-29

Applicant: Leslie E. Cline ,  Xia Dai ,  Varghese George ,  Robert L. Farrell

Inventor： Leslie E. Cline ,  Xia Dai ,  Varghese George ,  Robert L. Farrell

IPC: G06F1/26

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A selectable control over multiple clock frequency/voltage level combinations that can be activated in a processor. A table can be placed in hardware that defines multiple combinations of CPU clock frequency and CPU operating voltage. By placing the table in hardware, it can be assured that all the various combinations will work for the particular processor device. Software can then be used to select a combination from this table, to control the actual frequency/voltage combination that is being implemented at a given time. This allows dynamic control over the power/performance tradeoff, so that the system can see maximum power savings consistent with acceptable performance, as operating and environmental considerations continue to change the most desirable selections.

Abstract translation: 可以在处理器中激活的多个时钟频率/电压电平组合的可选择控制。 一个表可以放置在硬件中，定义了CPU时钟频率和CPU工作电压的多种组合。 通过将表放置在硬件中，可以确保所有各种组合都适用于特定的处理器设备。 然后可以使用软件从该表中选择组合，以控制在给定时间正在实施的实际频率/电压组合。 这允许对功率/性能的权衡进行动态控制，使得系统可以看到与可接受的性能一致的最大功率节省，因为操作和环境考虑继续改变最理想的选择。