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    Integrated circuit with different channel materials for P and N channel transistors and method therefor
    61.
    发明申请
    Integrated circuit with different channel materials for P and N channel transistors and method therefor 有权
    用于P和N沟道晶体管的不同沟道材料的集成电路及其方法

    公开(公告)号：US20070241403A1

    公开(公告)日：2007-10-18

    申请号：US11402395

    申请日：2006-04-12

    申请人： Voon-Yew Thean ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Victor Vartanian ,  Ted White

    发明人： Voon-Yew Thean ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Victor Vartanian ,  Ted White

    IPC分类号： H01L29/76 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/1203

    摘要： A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.

    摘要翻译： 衬底包括第一区域和第二区域。 第一区域包括III族氮化物层，第二区域包括第一半导体层。 在III族氮化物层上形成第一晶体管（例如n型晶体管），并且在第一半导体层上形成第二晶体管（例如p型晶体管）。 III族氮化物层可以是氮化铟。 在第一区域中，衬底可以包括第二半导体层，在第二半导体层上的渐变过渡层，以及过渡层上的缓冲层，其中III族氮化物层在缓冲层之上。 在第二区域中，衬底可以包括第二半导体层和在第二半导体层上的绝缘层，其中第一半导体层在绝缘层之上。

    Method for making a semiconductor device with strain enhancement
    62.
    发明授权
    Method for making a semiconductor device with strain enhancement 有权
    制造具有应变增强的半导体器件的方法

    公开(公告)号：US07282415B2

    公开(公告)日：2007-10-16

    申请号：US11092291

    申请日：2005-03-29

    申请人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

    发明人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

    摘要： A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

    摘要翻译： 通过提供半导体衬底和具有侧壁的上覆控制电极来形成具有应变增强的半导体器件。 在控制电极的侧壁附近形成绝缘层。 注入半导体衬底和控制电极以形成第一和第二掺杂电流电极区域，第一和第二掺杂电流电极区域中的每一个的一部分被驱动以在第一和第二掺杂电流电极区域的沟道区域中的绝缘层和控制电极之下 半导体器件。 第一和第二掺杂电流电极区域除了在控制电极和绝缘层之下除去分别形成第一和第二沟槽的半导体衬底外。 在第一和第二沟槽内形成有相对于半导体衬底具有不同晶格常数的原位掺杂材料，用作半导体器件的第一和第二电流电极。

    Graded semiconductor layer
    63.
    发明授权
    Graded semiconductor layer 有权
    分级半导体层

    公开(公告)号：US07241647B2

    公开(公告)日：2007-07-10

    申请号：US10919952

    申请日：2004-08-17

    申请人： Mariam G. Sadaka ,  Shawn G. Thomas ,  Ted R. White ,  Chun-Li Liu ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean

    发明人： Mariam G. Sadaka ,  Shawn G. Thomas ,  Ted R. White ,  Chun-Li Liu ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78687 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66742

    摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.

    摘要翻译： 一种形成半导体器件的方法。 该方法包括形成用于形成应变硅层的模板层。 在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。 当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。 由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

    Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer
    68.
    发明授权
    Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer 有权
    形成包括形成栅电极层并形成图案化掩模层的电子器件的工艺

    公开(公告)号：US07737018B2

    公开(公告)日：2010-06-15

    申请号：US11671748

    申请日：2007-02-06

    申请人： Leo Mathew ,  Voon-Yew Thean ,  Vishal P. Trivedi

    发明人： Leo Mathew ,  Voon-Yew Thean ,  Vishal P. Trivedi

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28123 ,  H01L21/2652 ,  H01L21/32139 ,  H01L29/4966

    摘要： A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer is formed prior to forming the gate electrode layer, and a portion of the gate dielectric layer is exposed after removing the patterned masking layer and prior to forming another masking layer. A portion of the gate electrode layer remains covered during a process where some or all of the portion would be otherwise removed or consumed. By forming the electronic device using such a process, damage to the gate electrode structure while performing subsequent processing can be significantly reduced.

    摘要翻译： 形成电子器件的工艺可以包括形成栅极电极层并形成图案化掩模层。 在第一方面，在去除栅极电极层的基本上所有下部之前进行处理操作。 在第二方面，在形成栅极电极层之前形成栅极电介质层，并且在去除图案化掩模层之后并且在形成另一个掩模层之前，一部分栅极电介质层被曝光。 在其中将部分或全部部分将被去除或消耗的过程中，栅电极层的一部分保持覆盖。 通过使用这种处理形成电子器件，可以显着地减少执行后续处理时对栅电极结构的损坏。

    Modulation of Tantalum-Based Electrode Workfunction
    69.
    发明申请
    Modulation of Tantalum-Based Electrode Workfunction 审中-公开
    钽电极工作功能的调制

    公开(公告)号：US20090286387A1

    公开(公告)日：2009-11-19

    申请号：US12122178

    申请日：2008-05-16

    申请人： David C. Gilmer ,  Srikanth B. Samavedam ,  James K. Schaeffer ,  Voon-Yew Thean

    发明人： David C. Gilmer ,  Srikanth B. Samavedam ,  James K. Schaeffer ,  Voon-Yew Thean

    IPC分类号： H01L21/28 ,  H01L21/4763 ,  H01L21/3205

    CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4975

    摘要： A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (14) over a gate dielectric layer (12) and then selectively introducing nitrogen into the portions of the first conductive layer (14) in the PMOS device region (1), either by annealing (42) a nitrogen-containing diffusion layer (22) formed in the PMOS device region (1) or by performing an ammonia anneal process (82) while the NMOS device region (2) is masked. By introducing nitrogen into the first conductive layer (14), the work function is modulated toward PMOS band edge.

    摘要翻译： 一种半导体工艺和装置，通过在栅介质层（12）上形成第一导电层（14）制造金属栅电极，然后选择性地将氮引入PMOS器件区域（1）中的第一导电层（14）的部分 ），通过在形成于PMOS器件区域（1）中的含氮扩散层（22）退火（42），或者在NMOS器件区域（2）被掩蔽的同时执行氨退火工艺（82）。 通过将氮引入到第一导电层（14）中，功函数被调制到PMOS带边缘。