公开(公告)号：US20050149893A1

公开(公告)日：2005-07-07

申请号：US10749581

申请日：2003-12-31

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Methods, data processing systems, and program products supporting multi-cycle simulation are disclosed. According to one method, a configuration database including at least one data structure representing an instance of a Dial entity is received. The instance of the Dial entity has at least an input, an output, and at least one associated latch within a digital design. A value of the output of the instance of the Dial entity controls a value stored within the associated latch. A control file is also received. The control file indicates that at least one associated latch data structure is to be inserted within the configuration database to represent the latch during multi-cycle simulation. In response to receipt of the configuration database and the control file, the configuration database is processed with reference to the control file to insert within the configuration database at least one latch data structure and to associate, within the configuration database, the at least one latch data structure with the instance of the Dial entity.

摘要翻译： 公开了支持多循环模拟的方法，数据处理系统和程序产品。 根据一种方法，接收包括表示Dial实体的实例的至少一个数据结构的配置数据库。 Dial实体的实例在数字设计中至少具有输入，输出和至少一个相关联的锁存器。 Dial实例的实例的输出值控制存储在相关联的锁存器内的值。 还收到一个控制文件。 控制文件指示在多循环模拟期间，至少一个相关联的锁存数据结构将被插入配置数据库中以表示锁存器。 响应于接收到配置数据库和控制文件，参考控制文件来处理配置数据库，以在配置数据库内插入至少一个锁存数据结构，并且在配置数据库内将至少一个锁存器 数据结构与Dial实体的实例。

公开(公告)号：US20050149309A1

公开(公告)日：2005-07-07

申请号：US10750590

申请日：2003-12-31

申请人： Bradley Nelson ,  Wolfgang Roesner ,  Derek Williams

发明人： Bradley Nelson ,  Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest.

摘要翻译： 根据指定用于数字设计的仿真的跟踪阵列的方法，模拟模型中的一个或多个实体用一个或多个硬件描述语言（HDL）文件中的一个或多个语句来指定。 另外，在一个或多个HDL文件中的一个或多个语句中指定用于存储通过模拟仿真模型生成的数据的跟踪数组。 随后可以处理HDL文件以创建包含设计实体内的至少一个设计实体和跟踪阵列的模拟模型，用于存储关于所关心的指定信号的跟踪数据。

公开(公告)号：US06826732B2

公开(公告)日：2004-11-30

申请号：US10425075

申请日：2003-04-28

申请人： Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F1750

CPC分类号： G06F17/5022 ,  G06F17/5045

摘要： A configuration database associated with a hardware system stores at least one data structure defining a Dial instance and a mapping between each of a plurality of possible input values of the Dial instance and a respective one of a corresponding plurality of output values, where the plurality of output values controls which of a plurality of different possible latch values is placed in a hardware latch to configure the hardware system. The configuration database further indicates an association between the Dial instance and the hardware latch. In response to receipt of a request specifying an input value for the Dial instance, the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value is obtained based upon the output value and the association. The latch value is then provided to the hardware system to set the hardware latch to the desired latch value.

摘要翻译： 与硬件系统相关联的配置数据库存储定义Dial实例的至少一个数据结构以及Dial实例的多个可能的输入值中的每一个与相应的多个输出值中的相应的一个之间的映射，其中多个 输出值控制多个不同可能的锁存值中的哪一个被放置在硬件锁存器中以配置硬件系统。 配置数据库还指示Dial实例和硬件锁存器之间的关联。 响应于接收到指定Dial实例的输入值的请求，访问配置数据库以基于映射来确定Dial实例的输出值。 此外，基于输出值和关联来获得锁存值。 然后将锁存值提供给硬件系统，以将硬件锁存器设置为所需的锁存值。

公开(公告)号：US06763505B2

公开(公告)日：2004-07-13

申请号：US10116607

申请日：2002-04-04

申请人： Jason Raymond Baumgartner ,  Robert Lowell Kanzelman ,  Wolfgang Roesner

发明人： Jason Raymond Baumgartner ,  Robert Lowell Kanzelman ,  Wolfgang Roesner

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced. The coloring information of the original circuit, plus information as to the exact nature of the phase abstraction performed, is then used to transform the phase abstracted trace to one which resembles a trace of the circuit without phase abstraction.

摘要翻译： 提供了一种用于自动使用相位抽象以用于电路设计的增强验证的装置和方法。 利用该装置和方法，锁存器是“彩色的”，即根据从电路设计的时钟树获得的信息被分类成不同类型。 时钟树原语包含足够的信息，将时钟分类到各自的相位，并确定哪些锁存器是门控锁存器。 在对锁存器进行着色时，门控锁存器在电路设计中被替换为具有自由运行时钟，多路复用器和L1到Ln锁存器的序列，以通过数据路径提供反馈路径。 这允许门控锁存器被相位抽取，而不会损失所得到的跟踪中门控锁存器的“选通”功能。 一旦锁存器以这种方式着色，相位抽象就在彩色电路设计上执行。 然后对相抽象网表进行验证，并生成跟踪。 原始电路的着色信息，以及执行相位抽象的确切性质的信息，然后用于将相位抽象曲线转换为类似于没有相位抽象的电路轨迹。

公开(公告)号：US06740910B2

公开(公告)日：2004-05-25

申请号：US10352830

申请日：2003-01-28

申请人： Wolfgang Roesner ,  Richard Johannes Luyken ,  Johannes Kretz

发明人： Wolfgang Roesner ,  Richard Johannes Luyken ,  Johannes Kretz

IPC分类号： H01L2976

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/78642 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512 ,  Y10S977/938

摘要： The gate region of a field effect transistor comprises at least one through hole wherein a nanoelement is provided which is electrically coupled to the source and the drain. The nanoelement may have the conductance thereof controlled by means of the gate, such that the nanoelement forms a channel region of the field effect transistor.

摘要翻译： 场效应晶体管的栅极区域包括至少一个通孔，其中提供了与源极和漏极电耦合的纳米元件。 纳米元件可以通过栅极控制其电导，使得纳米元件形成场效应晶体管的沟道区。

公开(公告)号：US06223142B1

公开(公告)日：2001-04-24

申请号：US09190861

申请日：1998-11-09

申请人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams ,  Bryan R. Hunt

发明人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams ,  Bryan R. Hunt

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for incrementally compiling instrumentation logic into a simulation model of a digital circuit design. According to the present invention, a simulation model that includes a design entity file of a digital circuit design is generated. Next, an instrumentation entity file is associated with the design entity file, thereby producing an instrumented design entity file. Finally, and during the process of compiling the simulation model, for the instrumented design entity file: searching for a consistent and previously compiled version of said instrumented design entity file. In response to finding a consistent and previously compiled version, loading the consistent and previously compiled version into the simulation model. In response to finding no consistent and previously compiled version, loading and compiling the instrumented design entity file.

摘要翻译： 公开了一种利用硬件描述语言的表现力来逐步编译仪表逻辑到数字电路设计的仿真模型中的方法和系统。 根据本发明，生成包括数字电路设计的设计实体文件的仿真模型。 接下来，仪器实体文件与设计实体文件相关联，从而生成一个被检测的设计实体文件。 最后，在编译仿真模型的过程中，对于仪表化设计实体文件：搜索一致和先前编译的所述仪表化设计实体文件的版本。 为了找到一致和先前编译的版本，将一致和先前编译的版本加载到仿真模型中。 响应于找不到一致和先前编译的版本，加载和编译仪表化的设计实体文件。

公开(公告)号：US5540977A

公开(公告)日：1996-07-30

申请号：US365932

申请日：1994-12-29

申请人： Thomas Vogelsang ,  Wolfgang Roesner

发明人： Thomas Vogelsang ,  Wolfgang Roesner

IPC分类号： H01L29/06 ,  G11C11/401 ,  H01L21/28 ,  H01L29/15 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/88 ,  H01L45/00 ,  H01L51/30

CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/16 ,  H01L45/00 ,  H01L51/0046 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A microelectronic component has a substrate on which a layer structure and at least two contact structures are arranged. The layer structure and the contact structures are electrically connected to one another but are electrically insulated from the substrate. The layer structure is formed by one layer of individual elements that are electrically connected to one another via quantum-mechanical tunnel contacts.

摘要翻译： 微电子部件具有其上布置有层结构和至少两个接触结构的基板。 层结构和接触结构彼此电连接，但与基板电绝缘。 层结构由通过量子力学隧道接触彼此电连接的一层单独元件形成。

公开(公告)号：US20130092977A1

公开(公告)日：2013-04-18

申请号：US13274411

申请日：2011-10-17

申请人： Holger Huesken ,  Anton Mauder ,  Hans-Joachim Schulze ,  Wolfgang Roesner

发明人： Holger Huesken ,  Anton Mauder ,  Hans-Joachim Schulze ,  Wolfgang Roesner

IPC分类号： H01L29/739 ,  H01L21/331 ,  H01L29/73

CPC分类号： H01L29/0688 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/08 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66143 ,  H01L29/66325 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/872

摘要： A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.

摘要翻译： 提供功率半导体二极管。 功率半导体二极管包括具有第一导电类型的第一发射极区域，第二导电类型的第二发射极区域和布置在第一发射极区域和第二发射极区域之间的第一导电类型的漂移区域的半导体衬底。 漂移区域与第二发射极区域形成pn结。 第一发射极金属化与第一发射极区域接触。 第一发射极区域包括第一导电类型的第一掺杂区域和第一导电类型的第二掺杂区域。 第一掺杂区与第一发射极金属化形成欧姆接触，第二掺杂区与第一发射极金属化形成非欧姆接触。 第二发射极金属化与第二发射极区域接触。

公开(公告)号：US08160857B2

公开(公告)日：2012-04-17

申请号：US12336019

申请日：2008-12-16

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek E. Williams

IPC分类号： G06F9/455

CPC分类号： G06F17/5022

摘要： In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executable model of the design is built. Building the model includes compiling the HDL file(s) specifying the plurality of hierarchically arranged design entities defining the design and instantiating at least one instance of each of the plurality of hierarchically arranged design entities, and further includes instantiating an instance of the instrumentation entity within an instance of a particular design entity among the plurality of design entities and, based upon a reference in an instrumentation statement in the one or more HDL files, logically attaching an input of the instance of the instrumentation entity to an input source within the design that is outside the scope of the particular design entity.

摘要翻译： 响应于接收到指定多个分层布置的设计实体的定义待仿真设计的HDL文件，并指定用于监视设计的模拟操作的仪器实体，构建了该设计的仪表化仿真可执行模型。 构建模型包括编译指定定义设计的多个分层布置的设计实体的HDL文件，并且实例化多个分级排列的设计实体中的每一个的至少一个实例，并且还包括实例化所述多个分层布置设计实体内的所述检测实体的实例 所述多个设计实体中的特定设计实体的实例，并且基于所述一个或多个HDL文件中的检测语句中的引用，将所述检测实体的实例的输入逻辑地附加到所述设计中的输入源， 不在特定设计实体的范围之内。

公开(公告)号：US20100090264A1

公开(公告)日：2010-04-15

申请号：US12249060

申请日：2008-10-10

申请人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

发明人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

摘要翻译： 一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。 互连件包括布置在半导体本体表面下方的金属体。 接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。 接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。 还公开了其它方法，装置和系统。