公开(公告)号：US20090092147A1

公开(公告)日：2009-04-09

申请号：US12010762

申请日：2008-01-29

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Tasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Tasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

IPC分类号： H04L12/28

CPC分类号： H04L47/6255 ,  H04L12/44 ,  H04L47/10 ,  H04L47/2458 ,  H04L47/30 ,  H04L47/522 ,  H04L49/205 ,  H04L49/3018 ,  H04L49/351

摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

摘要翻译： 由CPU1生成的发送包被保存在缓冲器100a（100b）中。 从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。 应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。 如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。 如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于 传输分组的传输分组优先于传送分组传送到以太网820a或820b。 这防止了传送缓冲器装置溢出。

公开(公告)号：US07111187B2

公开(公告)日：2006-09-19

申请号：US10701447

申请日：2003-11-06

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F1/04

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.

摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 与原始时钟信号K锁相并且具有预定占空比的至少一个第二时钟信号K 1 1和其操作时序被第二时钟信号K _{1 <1>，并且由至少一对逻辑器件之间提供的接口的操作时序由时钟信号K 1 1同步地控制。}

公开(公告)号：US20060015231A1

公开(公告)日：2006-01-19

申请号：US11094660

申请日：2005-03-31

申请人： Kentaro Yoshimura ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Yuichiro Morita ,  Yoshiaki Takahashi ,  Kenichi Kurosawa ,  Toshimichi Minowa ,  Masatoshi Hoshino ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shoji Sasaki

发明人： Kentaro Yoshimura ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Yuichiro Morita ,  Yoshiaki Takahashi ,  Kenichi Kurosawa ,  Toshimichi Minowa ,  Masatoshi Hoshino ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shoji Sasaki

IPC分类号： G06F19/00

CPC分类号： B60W30/00 ,  B60K6/46 ,  B60K6/52 ,  B60L3/0023 ,  B60L3/003 ,  B60L3/0076 ,  B60L3/0092 ,  B60L15/2009 ,  B60L2240/12 ,  B60L2240/20 ,  B60L2240/24 ,  B60L2240/423 ,  B60L2250/26 ,  B60T7/12 ,  B60W10/04 ,  B60W10/06 ,  B60W10/08 ,  B60W10/10 ,  B60W10/18 ,  B60W10/20 ,  B60W20/00 ,  B60W40/08 ,  B60W40/10 ,  B60W50/02 ,  B60W50/0225 ,  B60W50/04 ,  B60W2510/20 ,  B60W2510/202 ,  B60W2520/14 ,  B60W2540/10 ,  B60W2540/12 ,  B60W2550/20 ,  B62D5/046 ,  B62D5/0481 ,  B62D6/00 ,  G06F11/0796 ,  Y02T10/6217 ,  Y02T10/6265 ,  Y02T10/6286 ,  Y02T10/645 ,  Y02T10/72 ,  Y02T10/7275 ,  Y02T90/16

摘要： A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network. The actuator controller includes a control target value generating unit for generating a control target value based on the sensor signals taken in by the sensor controller and received by the actuator controller via the network when the control target value generated by the command controller is abnormal, and controls the actuator in accordance with the control target value generated by the control target value generating unit.

公开(公告)号：US20050068897A1

公开(公告)日：2005-03-31

申请号：US10921879

申请日：2004-08-20

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

IPC分类号： H04L12/70 ,  G06F13/00 ,  H04L1/00 ,  H04L29/06 ,  H04M11/00

CPC分类号： H04L69/16 ,  H04L49/90 ,  H04L69/161 ,  H04L69/162 ,  H04L69/22

摘要： A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

摘要翻译： 包括CPU，存储器和分组通信电路的分组通信装置充当远程监视和控制受控对象的网络连接受控对象和网络终端之间的接口，并且在 受控对象和网络终端还包括作为用于执行校验和计算以检查分组错误和复制操作的硬件单元的复制和操作单元。 复制和操作单元在存储器中形成并由分组通信电路使用的发送缓冲器/接收缓冲器与由通信处理程序使用的工作区域之间同时执行分组数据复制操作和校验和计算，从而减少 加载CPU并增加通信处理速度。

公开(公告)号：US20050062749A1

公开(公告)日：2005-03-24

申请号：US10983757

申请日：2004-11-09

申请人： Yasuhiro Nakatsuka ,  Tetsuya Shimomura ,  Manabu Jyou ,  Yuichiro Morita ,  Takashi Hotta ,  Kazushige Yamagishi ,  Yutaka Okada

发明人： Yasuhiro Nakatsuka ,  Tetsuya Shimomura ,  Manabu Jyou ,  Yuichiro Morita ,  Takashi Hotta ,  Kazushige Yamagishi ,  Yutaka Okada

IPC分类号： G06F13/16 ,  G06F3/153 ,  G06F12/00 ,  G06F12/04 ,  G09G5/39 ,  G06F15/167 ,  G06F13/00

CPC分类号： G09G5/39 ,  G09G2360/125

摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

摘要翻译： 多媒体数据处理系统的基本部分包括CPU 1100，图像显示单元2100，统一存储器1200，系统总线1920和连接到系统总线的设备1300,1400和1500。 在这种配置中，CPU形成在安装在包括指令处理单元1110和显示控制单元1140的单个硅晶片上的LSI上。主存储区域1210和显示区域1220存储在统一存储器内。 与用于连接LSI和输入/输出设备的系统总线无关地提供用于连接对应的LSI和统一存储器的统一存储器端口1910。 统一的存储器端口可以比系统总线更快地驱动。

公开(公告)号：US5680637A

公开(公告)日：1997-10-21

申请号：US599856

申请日：1996-02-13

申请人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Hiromichi Yamada ,  Hideo Maejima

发明人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Hiromichi Yamada ,  Hideo Maejima

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30189 ,  G06F9/30043 ,  G06F9/30079 ,  G06F9/38 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3885

摘要： A RISC processor is arranged to reduce a code size, make the hardware less complicated, execute a plurality of operations for one machine cycle, and enhance the performance. The processor is capable of executing N instruction each having a short word length for indicating a single operation or an instruction having a long word length for indicating M (N

摘要翻译： RISC处理器被设置为减少代码大小，使硬件更不复杂，对一个机器周期执行多个操作，并提高性能。 处理器能够执行每个具有用于指示单个操作的短字长的N指令或具有用于指示M（N

公开(公告)号：US5542083A

公开(公告)日：1996-07-30

申请号：US460601

申请日：1995-06-02

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F1/10 ,  H03K5/156 ,  H03L7/18 ,  G06F1/04

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时 至少一对逻辑器件由时钟信号K1同步控制。

公开(公告)号：US5526509A

公开(公告)日：1996-06-11

申请号：US386757

申请日：1995-02-10

申请人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

发明人： Toshio Doi ,  Takeshi Takemoto ,  Yasuhiro Nakatsuka

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0808 ,  G06F12/1063

摘要： A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

公开(公告)号：US5287465A

公开(公告)日：1994-02-15

申请号：US549916

申请日：1990-07-09

申请人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

发明人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/177 ,  G06F9/00

CPC分类号： G06F9/30189 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

摘要： When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed. Further, the parallel processing apparatus making great account of compatibility of a great part of software reads out m instructions without using the processing state flag, decodes the m instructions, checks whether a branch instruction exists in the k-th instruction, then executes the first to the (k+1)-th instructions in k+1 arithmetic units, and prevent execution of the (k+ 2)-th to m-th instructions. By executing the k-th branch instruction, the parallel processing apparatus calculates an address nm+h of its branch destination, performs calculation to check whether the condition is satisfied or not, then prevents execution of instructions of addresses nm to nm+h-1, and executes instructions of addresses nm+h to (n+1)m. In this way, the parallel processing apparatus executes a plurality of instructions and successively executes branch instructions.

摘要翻译： 当执行常规软件的连续处理时，并行处理装置将处理状态判别标志关闭，一次将程序数增加1，读出一个指令，并在运算单元中处理该指令。 当执行新软件的并行处理时，并行处理装置将处理状态判别转为一次，一次增加程序数m，读出m个指令，并对m个运算单元中的m个指令进行并行处理。 为了选择上述两种处理之一，添加具有改变处理状态判别标志的功能的识别切换指令。 指令根据处理状态判别标志在算术单元中进行处理。 以这种方式，连续处理和并行处理具有兼容性并且被选择性地执行。 此外，大量软件的兼容性的并行处理装置在不使用处理状态标志的情况下读出m个指令，对m个指令进行解码，检查第k个指令中是否存在转移指令，然后执行第一 到第k + 1个算术单元中的第（k + 1）个指令，并且防止执行第（k + 2）至第m指令。 通过执行第k个分支指令，并行处理装置计算其分支目的地的地址nm + h，执行计算以检查条件是否满足，然后防止执行地址nm到nm + h-1的指令 并且执行地址nm + h至（n + 1）m的指令。 以这种方式，并行处理装置执行多个指令，并连续执行分支指令。

公开(公告)号：US5274829A

公开(公告)日：1993-12-28

申请号：US114720

申请日：1987-10-28

申请人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh ,  Hideo Maejima

发明人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh ,  Hideo Maejima

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F15/78 ,  G06F1/00

CPC分类号： G06F9/268 ,  G06F9/26 ,  G06F9/328

摘要： A data processing apparatus which allows a large number of micro instructions to be read at high speeds by storing frequently used micro instructions in the on-chip ROM and those less frequently used in the off-chip memory. From the address of the micro instruction to be accessed, it is determined whether the micro instruction is stored in the on-chip ROM or the off-chip memory, and the micro instruction is accessed on the basis of this determination. A cache memory may also be provided on the chip for providing high speed repeat access to micro instructions stored in the off-chip memory.

摘要翻译： 一种数据处理装置，其通过将经常使用的微指令存储在片上ROM中以及在片外存储器中较少使用的微指令，允许以高速读取大量微指令。 根据要访问的微指令的地址，确定微指令是存储在片上ROM还是片外存储器中，并且基于该确定来访问微指令。 还可以在芯片上提供高速缓冲存储器，以提供对存储在片外存储器中的微指令的高速重复访问。