公开(公告)号：US20070069391A1

公开(公告)日：2007-03-29

申请号：US11528841

申请日：2006-09-27

Applicant: Alex Gritti

Inventor： Alex Gritti

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2924/00012

Abstract: A stacked die semiconductor package includes: a substrate, having a first surface and an opposite surface thereto; a plurality of dice, structured for being stacked one on top of the other on the first surface of the substrate, including at least a first die which is mounted closest to the first surface, a second die mounted thereupon and having a larger footprint area than the first die, and a top die having a smaller footprint area than the underlying die thereof, and each having a plurality of contact pads and a plurality of wires for electrically connecting the dice to the first surface of the substrate; at least one interposer between the plurality of dice; advantageously, said top die is electrically directly connected to one of the underlying dice. A method for the assembly of a stacked die semiconductor package is provided.

Abstract translation: 叠层半导体封装包括：具有第一表面和与其相反表面的衬底; 多个骰子，被构造成在基板的第一表面上堆叠在另一个之上，包括至少安装在最靠近第一表面的第一模具，安装在其上的第二模具，并且具有比第一模具更大的占地面积 第一模具和顶部模具具有比其下面的芯片更小的占地面积，并且每个具有多个接触焊盘和用于将裸片电连接到衬底的第一表面的多个电线; 所述多个骰子中的至少一个插入件; 有利地，所述顶部管芯电气地直接连接到其中一个底部管芯。 提供了一种用于组装堆叠管芯半导体封装的方法。

公开(公告)号：US20070027946A1

公开(公告)日：2007-02-01

申请号：US11190501

申请日：2005-07-26

Applicant: Giuseppe Visalli ,  Francesco Pappalardo

Inventor： Giuseppe Visalli ,  Francesco Pappalardo

IPC: G06F7/50

CPC classification number: G06F7/74 ,  G06F7/485

Abstract: A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

Abstract translation: 一种用于从包括实际加法输入或至少一个较早进位的操作数开始的加法器中估计传播载波的电路，该电路用独立的二进制数据对操作数执行统计电路操作。 优选地，该二进制流量是独立的和等能的或准等能的二进制流量，并且加法器是前导零预期逻辑整数加法器，其产生与执行的整数相加的结果相同数量的前导零的数字。 进位值可以由操作数的逻辑功能（例如，Karnaugh Map，Quine-McClusky）产生，作为覆盖逻辑功能中的所有1的操作数的逻辑组合。

公开(公告)号：US20070016735A1

公开(公告)日：2007-01-18

申请号：US11432301

申请日：2006-05-10

Applicant: Francesco Mastroianni ,  Antonino Mondello ,  Elena Cussotto ,  Massimiliano Mollichelli ,  Mauro Sali

Inventor： Francesco Mastroianni ,  Antonino Mondello ,  Elena Cussotto ,  Massimiliano Mollichelli ,  Mauro Sali

IPC: G06F12/00 ,  G06F13/28 ,  G06F13/00 ,  G11C16/04 ,  G11C11/34

CPC classification number: G11C16/22 ,  G06F12/1433 ,  G06F21/6209 ,  G06F21/79 ,  G06F2212/2022

Abstract: A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.

Abstract translation: 闪存类型的非易失性存储器件包括用于存储数据的第一存储器单元，用于存储第一存储器单元的保护信息的第二存储器单元，以及用于更新保护信息的电路，其包括用于写入多个版本的电路 第二存储器单元中的保护信息，以及用于识别当前版本的保护信息的电路。

公开(公告)号：US20060267823A1

公开(公告)日：2006-11-30

申请号：US11420592

申请日：2006-05-26

Applicant: Carlo Pinna ,  Sergio Pernici ,  Angelo Nagari

Inventor： Carlo Pinna ,  Sergio Pernici ,  Angelo Nagari

IPC: H03M3/00

CPC classification number: H03M3/332 ,  H03M3/424 ,  H03M3/454

Abstract: A single-ended or differential single-stage, or multi-stage sigma-delta analog-to-digital converter includes at least one switched-capacitor integrator comprising a switched-capacitor network receiving as input a signal to be sampled, and an amplifier coupled in cascade to the switched-capacitor network. A circuit is coupled to the amplifier for feeding an analog dither signal to a virtual ground of the amplifier.

Abstract translation: 单端或差分单级或多级Σ-Δ模数转换器包括至少一个开关电容积分器，该开关电容积分器包括接收要被采样的信号作为输入的开关电容器网络，和放大器耦合 级联到开关电容网络。 电路耦合到放大器，用于将模拟抖动信号馈送到放大器的虚拟接地。

公开(公告)号：US20060261704A1

公开(公告)日：2006-11-23

申请号：US11409125

申请日：2006-04-21

Applicant: Luca Battaglin ,  Pietro Gallina ,  Giancarlo Saba ,  Giancarlo Zinco ,  Claudio Diazzi ,  Vittorio Peduto

Inventor： Luca Battaglin ,  Pietro Gallina ,  Giancarlo Saba ,  Giancarlo Zinco ,  Claudio Diazzi ,  Vittorio Peduto

IPC: H01L41/09

CPC classification number: H01L41/042

Abstract: The invention relates to a circuit for highly efficient driving of piezoelectric loads, comprising a linear driving circuit portion connected to the load through an inductive-resistive connection whereto a voltage waveform is applied. Advantageously, the circuit comprises further respective circuit portions, structurally independent, connected in turn to the inductive-resistive connection through respective inductors to supply a considerable fraction of the overall current required by the load in the transient and steady state respectively.

公开(公告)号：US20060214913A1

公开(公告)日：2006-09-28

申请号：US11290136

申请日：2005-11-30

Applicant: Gianluca Pedrazzini ,  Enrico Chiesa ,  Fabio Pasolini

Inventor： Gianluca Pedrazzini ,  Enrico Chiesa ,  Fabio Pasolini

IPC: G09G5/08

CPC classification number: G06F3/03543 ,  G06F3/0383

Abstract: A manual pointing device for a computer system, the device having at least one key that can be actuated manually by a user, and a click-event detection module coupled to the key for detecting actuation thereof. The click-event detection module is provided with an inertial sensor for detecting mechanical stresses generated by actuation of the key.

Abstract translation: 一种用于计算机系统的手动定位装置，该装置具有可由用户手动致动的至少一个键以及耦合到键的用于检测其致动的点击事件检测模块。 点击事件检测模块设置有用于检测由钥匙的致动产生的机械应力的惯性传感器。

公开(公告)号：US20060186965A1

公开(公告)日：2006-08-24

申请号：US11337722

申请日：2006-01-23

Applicant: Tino Copani ,  Santo Smerzi ,  Giovanni Girlando ,  Giuseppe Palmisano

Inventor： Tino Copani ,  Santo Smerzi ,  Giovanni Girlando ,  Giuseppe Palmisano

IPC: H03F3/45 ,  H03G3/12

CPC classification number: H03F3/45174

Abstract: A converter is for a differential input signal into a single-ended output signal and may include a differential pair of identical first and second transistors driven by the differential input signal, and a circuit for filtering DC components, connected between the current terminal of the second transistor not in common with the first transistor of the differential pair and an output node of the converter on which the single-ended output signal is generated. The converter generates a single-ended signal without employing a transformer, in lieu thereof the converter may include a current generator biasing the differential pair by of third and fourth output transistors, in a current mirror configuration, connected in series with the first and second transistors, respectively. The converter may also include degeneration resistors of the transistors of the current mirror, dimensioned such that the gains of the converter for each of the two input nodes of the differential signal are equal and of opposite sign.

Abstract translation: A转换器用于将差分输入信号转换为单端输出信号，并且可以包括由差分输入信号驱动的相同的第一和第二晶体管的差分对，以及用于滤波直流分量的电路，连接在第二 不同于差分对的第一晶体管的晶体管和其上产生单端输出信号的转换器的输出节点。 转换器产生单端信号而不使用变压器，代替其可以包括电流发生器，该电流发生器通过第三和第四输出晶体管以与第一和第二晶体管串联连接的电流镜配置来偏置差分对 ， 分别。 转换器还可以包括电流镜的晶体管的退化电阻，其尺寸使得差分信号的两个输入节点中的每一个的转换器的增益相等并且具有相反的符号。

公开(公告)号：US20060186434A1

公开(公告)日：2006-08-24

申请号：US11279967

申请日：2006-04-17

Applicant: Angelo MAGRI' ,  Ferruccio FRISINA ,  Giuseppe FERLA ,  Marco CAMALLERI

Inventor： Angelo MAGRI' ,  Ferruccio FRISINA ,  Giuseppe FERLA ,  Marco CAMALLERI

IPC: H01L29/423 ,  H01L21/332

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712

Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

Abstract translation: 具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。 栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。 第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

公开(公告)号：US20060055472A1

公开(公告)日：2006-03-16

申请号：US11155877

申请日：2005-06-17

Applicant: Ivan Bietti ,  Riccardo Tonietto

Inventor： Ivan Bietti ,  Riccardo Tonietto

IPC: H03K3/03

CPC classification number: H03K3/0322

Abstract: A multi-phase oscillator is provided. Said multi-phase oscillator includes a plurality of resonator stages series-connected in an ordered closed loop. Each stage is used for providing one or more oscillating voltages corresponding to an oscillating current. The oscillating current includes a natural current that is generated by the stage and one or more injected currents from a previous stage in the closed loop. The oscillating voltages provided by all the stages have substantially the same frequency; on the other hand, the oscillating voltages provided by each stage and the previous oscillating voltages provided by the previous stage have a corresponding phase difference. The oscillator further includes a coupler between each stage and the previous stage; the coupler is used for generating the injected currents according to the previous oscillating voltages. The coupler includes transconductance means for transforming one or more voltages corresponding to the previous oscillating voltages into one or more currents corresponding to the injected currents; the coupler further includes shifting means for shifting the phase of the injected currents according to the corresponding phase difference. The shifting means includes filtering means for filtering the previous oscillating voltages into one or more corresponding filtered oscillating voltages to be supplied to the transconductance means.

Abstract translation: 提供了多相振荡器。 所述多相振荡器包括以有序闭环串联连接的多个谐振器级。 每个级用于提供对应于振荡电流的一个或多个振荡电压。 振荡电流包括由该级产生的自然电流和来自闭环中前一级的一个或多个注入电流。 所有级提供的振荡电压具有基本相同的频率; 另一方面，由各级提供的振荡电压和由前一级提供的先前的振荡电压具有对应的相位差。 振荡器还包括每个级与前一级之间的耦合器; 耦合器用于根据先前的振荡电压产生注入的电流。 耦合器包括跨导装置，用于将对应于先前振荡电压的一个或多个电压变换成对应于注入电流的一个或多个电流; 耦合器还包括根据相应的相位差移动注入电流的相位的移位装置。 移位装置包括滤波装置，用于将先前的振荡电压滤波成一个或多个相应的滤波后的振荡电压，以提供给跨导装置。

公开(公告)号：US20060038594A1

公开(公告)日：2006-02-23

申请号：US11141252

申请日：2005-05-31

Applicant: Tino Copani ,  Santo Smerzi ,  Giovanni Girlando ,  Giuseppe Palmisano

Inventor： Tino Copani ,  Santo Smerzi ,  Giovanni Girlando ,  Giuseppe Palmisano

IPC: H03K23/00

CPC classification number: H03K23/662

Abstract: A prescaling stage includes bistable circuit in turn including respective master and slave portions inserted between a first and a second voltage reference and feedback connected to each other. Each portion is provided with at least one differential stage supplied by the first voltage reference and connected, by a transistor stage, to the second voltage reference, as well as a differential pair of cross-coupled transistors, supplied by output terminals of the differential stage and connected, by the transistor stage, to the second voltage reference. Advantageously, each master and slave portion includes a degeneration capacitance inserted in correspondence with respective terminals of the transistors of the differential pair.

Abstract translation: 预分频级包括双稳态电路，其依次包括插入在第一和第二电压基准之间的相应主从部分和彼此连接的反馈。 每个部分设置有由第一参考电压供应并由晶体管级连接到第二参考电压的至少一个差分级，以及由差分级的输出端提供的交叉耦合晶体管的差分对 并通过晶体管级连接到第二电压基准。 有利地，每个主从部分包括与差分对的晶体管的各个端子相对应地插入的退化电容。