公开(公告)号：US12272750B2

公开(公告)日：2025-04-08

申请号：US18330604

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: G11C11/22 ,  G11C5/06 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

公开(公告)号：US12272634B2

公开(公告)日：2025-04-08

申请号：US18301757

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.

公开(公告)号：US12272631B2

公开(公告)日：2025-04-08

申请号：US18447008

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.

公开(公告)号：US12272600B2

公开(公告)日：2025-04-08

申请号：US17663302

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chang-Ting Chung ,  Yi-Hsiang Chao ,  Yu-Ting Wen ,  Kai-Chieh Yang ,  Yu-Chen Ko ,  Peng-Hao Hsu ,  Ya-Yi Cheng ,  Min-Hsiu Hung ,  Chun-Hsien Huang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/535

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

公开(公告)号：US12272595B2

公开(公告)日：2025-04-08

申请号：US17453872

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Che-Cheng Chang ,  Wen-Tung Chen ,  Yu-Cheng Liu ,  Horng-Huei Tseng

IPC: H01L21/768

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

公开(公告)号：US12272580B2

公开(公告)日：2025-04-08

申请号：US18403613

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jung Huang ,  Yung-Lin Hsu ,  Kuang Huan Hsu ,  Jeff Chen ,  Steven Huang ,  Yueh-Lun Yang

IPC: H01L21/677 ,  H01L21/67

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

公开(公告)号：US12272554B2

公开(公告)日：2025-04-08

申请号：US18227231

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Lin Wei ,  Ming-Hui Weng ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Yahru Cheng ,  Jr-Hung Li ,  Ching-Yu Chang ,  Tze-Liang Lee ,  Chi-Ming Yang

IPC: H01L21/033 ,  G03F1/22 ,  G03F7/00 ,  H01L21/308

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US12269141B2

公开(公告)日：2025-04-08

申请号：US18349491

申请日：2023-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Hsuan Lee ,  Ming-Shiuan She ,  Chen-Hao Wu ,  Chun-Hung Liao ,  Shen-Nan Lee ,  Teng-Chun Tsai

IPC: C08J9/26 ,  B24B37/10 ,  B24B37/24 ,  B32B3/10 ,  B32B3/12 ,  C09G1/02 ,  B32B5/00 ,  C08L53/00 ,  C08L75/04 ,  C08L77/00 ,  C08L81/06

Abstract: A method disclosed herein includes forming a polishing pad configured for a chemical-mechanical polishing (CMP) process and polishing a workpiece using the polishing pad and a CMP slurry. Forming the polishing pad includes forming an interpenetrating polymer network having a first phase and a second phase embedded in the first phase, removing the second phase from the interpenetrating polymer network, thereby forming a porous top pad that includes a network of pores embedded in the first phase, and adhering the porous top pad to a sub pad, thereby forming the polishing pad. The second phase is different from the first phase in composition, and the interpenetrating polymer network has a substantially periodic pattern. Surface roughness of the porous top pad is consistent during the polishing of the workpiece.

公开(公告)号：US20250113504A1

公开(公告)日：2025-04-03

申请号：US18981103

申请日：2024-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Kai SHIH ,  Kuo-Liang WANG

IPC: H01L23/522

Abstract: Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

公开(公告)号：US20250112137A1

公开(公告)日：2025-04-03

申请号：US18478592

申请日：2023-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Liu ,  Po-Yao Lin ,  Sing-Da Jiang ,  Tsunyen Wu ,  Kathy Wei Yan

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L25/065

Abstract: A method of manufacturing a device includes bonding a first die and a second die to a first side of a substrate, forming a stress buffer structure over the first die and the second die, where the stress buffer structure includes a first portion of a first via extending through a first insulating layer, a second portion of the first via extending through a second insulating layer, and a third portion of the first via extending through a third insulating layer, where the second portion of the first via is disposed between the first portion of the first via and the third portion of the first via, and where a diameter of the second portion of the first via is smaller than diameters of the first portion of the first via and the third portion of the first via, and depositing a metal layer over the stress buffer structure.