公开(公告)号：US20050112887A1

公开(公告)日：2005-05-26

申请号：US10977302

申请日：2004-10-29

Applicant: Junichi Muramoto

Inventor： Junichi Muramoto

IPC: H01L21/302 ,  B81C1/00 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/461

CPC classification number: B81C1/00047 ,  B81C1/00476 ,  B81C2201/0142 ,  B81C2201/117 ,  H01L21/3065 ,  H01L21/31116

Abstract: An etching process is provided. The etching process allows etching and removing with a sufficient rate, from a fine etching opening, a sacrificing layer and thereby can form a structure that has a large hollow portion or a complicatedly constituted space portion and furthermore a structure high in the aspect ratio with excellent shape accuracy and without deteriorating a surface state. In the etching process, a work is exposed to a processing fluid that contains an etching reaction species and the processing fluid is maintained in a state where it is flowed relative to the work. In this state, on a surface of the work, illumination light is intermittently illuminated to heat the work intermittently. Thereby, the processing fluid in the neighborhood of the work is intermittently heated and thereby expanded and contracted to etch. As the processing fluid, a substance that contains an etching reaction species and is in a super critical state can be preferably used.

Abstract translation: 提供蚀刻工艺。 蚀刻工艺允许从精细蚀刻开口，牺牲层以足够的速率进行蚀刻和去除，从而可以形成具有大的中空部分或复杂构造的空间部分的结构，并且还可以形成具有优异的纵横比的结构 形状精度并且不会使表面状态恶化。 在蚀刻工艺中，工件暴露于含有蚀刻反应物质的处理流体，并且处理流体保持在相对于工件流动的状态。 在这种状态下，在工件的表面上间歇地照明照明光以间歇地加热工件。 由此，工件附近的处理流体被间歇地加热，从而膨胀和收缩以进行蚀刻。 作为处理液，优选使用含有蚀刻反应物质并处于超临界状态的物质。

公开(公告)号：US20040141894A1

公开(公告)日：2004-07-22

申请号：US10755339

申请日：2004-01-13

Applicant: FUJITSU LIMITED ,  FUJITSU MEDIA DEVICES LIMITED

Inventor： Yoshihiro Mizuno ,  Satoshi Ueda ,  Osamu Tsuboi ,  Ippei Sawaki ,  Hisao Okuda ,  Fumio Yamagishi ,  Norinao Kouma

IPC: F28D007/00

CPC classification number: G02B26/0841 ,  B01D53/885 ,  B01J8/0453 ,  B01J8/0496 ,  B01J2208/00212 ,  B01J2208/00309 ,  B01J2208/025 ,  B81B2201/045 ,  B81B2203/0136 ,  B81C1/00142 ,  B81C1/00626 ,  B81C2201/0142 ,  C01B3/16 ,  C01B2203/0288 ,  C01B2203/045 ,  C01B2203/0485 ,  Y10S359/904

Abstract: A method of making a micromirror unit is provided. In accordance with the method, a micromirror unit is made from a material substrate having a multi-layer structure composed of silicon layers and at least one intermediate layer. The resulting micromirror unit includes a mirror forming base, a frame and a torsion bar. The method includes the following steps. First, a pre-torsion bar is formed by subjecting one of the silicon layers to etching. The obtained pre-torsion bar is rendered smaller in thickness than the mirror forming base and is held in contact with the intermediate layer. Then, the desired torsion bar is obtained by removing the intermediate layer contacting with the pre-torsion bar.

公开(公告)号：US06723659B2

公开(公告)日：2004-04-20

申请号：US09995588

申请日：2001-11-29

Applicant: Yoshihiro Mizuno ,  Satoshi Ueda ,  Osamu Tsuboi ,  Ippei Sawaki ,  Hisao Okuda ,  Fumio Yamagishi ,  Norinao Kouma

Inventor： Yoshihiro Mizuno ,  Satoshi Ueda ,  Osamu Tsuboi ,  Ippei Sawaki ,  Hisao Okuda ,  Fumio Yamagishi ,  Norinao Kouma

IPC: H01L21302

CPC classification number: G02B26/0841 ,  B01D53/885 ,  B01J8/0453 ,  B01J8/0496 ,  B01J2208/00212 ,  B01J2208/00309 ,  B01J2208/025 ,  B81B2201/045 ,  B81B2203/0136 ,  B81C1/00142 ,  B81C1/00626 ,  B81C2201/0142 ,  C01B3/16 ,  C01B2203/0288 ,  C01B2203/045 ,  C01B2203/0485 ,  Y10S359/904

Abstract: A method of making a micromirror unit is provided. In accordance with the method, a micromirror unit is made from a material substrate having a multi-layer structure composed of silicon layers and at least one intermediate layer. The resulting micromirror unit includes a mirror forming base, a frame and a torsion bar. The method includes the following steps. First, a pre-torsion bar is formed by subjecting one of the silicon layers to etching. The obtained pre-torsion bar is rendered smaller in thickness than the mirror forming base and is held in contact with the intermediate layer. Then, the desired torsion bar is obtained by removing the intermediate layer contacting with the pre-torsion bar.

Abstract translation: 提供了制造微镜单元的方法。 根据该方法，微镜单元由具有由硅层和至少一个中间层构成的多层结构的材料基板制成。 所得到的微镜单元包括反射镜形成基座，框架和扭杆。 该方法包括以下步骤。 首先，通过使一个硅层进行蚀刻来形成预扭杆。 所获得的预扭杆的厚度比反射镜形成基座的厚度小，并与中间层保持接触。 然后，通过去除与预扭杆接触的中间层来获得所需的扭力杆。

公开(公告)号：US20030124848A1

公开(公告)日：2003-07-03

申请号：US10265620

申请日：2002-10-08

Applicant: APPLIED MATERIALS, INC.

Inventor： Jeffrey D. Chinn ,  Robert Z. Bachrach

IPC: H01L021/302 ,  H01L021/461

CPC classification number: B81C1/00476 ,  B81C99/0065 ,  B81C2201/0142

Abstract: A method of determining the time to release of a movable feature in a multilayer substrate of silicon-containing materials including alternate layers of polysilicon and silicon oxide wherein a mass monitoring device determines the mass of a released feature, and the substrate is etched with anhydrous hydrogen fluoride until the substrate mass is equivalent to that of the released movable feature when the etch time is noted. A suitable mass monitoring device is a quartz crystal microbalance.

Abstract translation: 一种确定在包含多晶硅和氧化硅的交替层的含硅材料的多层衬底中释放可移动特征的时间的方法，其中质量监测装置确定释放特征的质量，并且用无水氢氧化物蚀刻衬底 氟化物，直到当注意到蚀刻时间时，衬底质量等于释放的可移动特征的质量。 合适的质量监测装置是石英晶体微量天平。

公开(公告)号：US5980767A

公开(公告)日：1999-11-09

申请号：US899864

申请日：1997-07-24

Applicant: Chishio Koshimizu ,  Kimihiro Higuchi

Inventor： Chishio Koshimizu ,  Kimihiro Higuchi

IPC: G01N21/68 ,  H01L21/302

CPC classification number: G01N21/68 ,  B81C1/00587 ,  B81C99/0065 ,  H01J37/32963 ,  H01J37/3299 ,  B81C2201/0142

Abstract: Disclosed herein is a method of detecting an end point of plasma process performed on an object, and a plasma process apparatus. The method includes the steps of detecting an emission spectrum over a wavelength region specific to C.sub.2 in the plasma, by optical detecting means, and determining the end point of the plasma process from the emission intensity of the emission spectrum detected by the optical detector. The apparatus has a process chamber, a pair of electrodes, a light-collecting device, an optical detector, and a determining device. The chamber has a monitor window. The electrodes are located in the process chamber. The first electrode is used to support the object. A high-frequency power is supplied between the electrodes to change a process gas into plasma. The light-collecting device collects the light from the plasma through the monitor window. The optical detector detects an emission spectrum from the light collected. The determining device determines the end point of the plasma process from the emission intensity of the emission spectrum detected. The monitor window is secured to the distal end of a cylindrical member protruding from the chamber. The member has a narrow gas passage for trapping a gas generated by the plasma process.

Abstract translation: 本文公开了一种检测对物体进行的等离子体处理的终点的方法和等离子体处理装置。 该方法包括以下步骤：通过光学检测装置检测等离子体中C2特有的波长区域上的发射光谱，并根据由光学检测器检测到的发射光谱的发射强度来确定等离子体处理的终点。 该装置具有处理室，一对电极，光收集装置，光学检测器和确定装置。 该房间有一个监视器窗口。 电极位于处理室中。 第一个电极用于支撑物体。 在电极之间提供高频电力以将处理气体改变为等离子体。 集光装置通过监视窗收集来自等离子体的光。 光学检测器从所收集的光线检测发射光谱。 确定装置根据检测到的发射光谱的发射强度确定等离子体处理的终点。 监视器窗口固定到从腔室突出的圆柱形构件的远端。 该构件具有用于捕获由等离子体工艺产生的气体的窄气体通道。

公开(公告)号：US20240208806A1

公开(公告)日：2024-06-27

申请号：US18393670

申请日：2023-12-22

Applicant: National Taiwan University

Inventor： Jun-Chau Chien ,  Wei-Yang Weng

IPC: B81C1/00 ,  B81B1/00 ,  C12M1/34 ,  C12M3/06

CPC classification number: B81C1/00539 ,  B81B1/002 ,  C12M23/16 ,  C12M41/30 ,  B81B2201/0214 ,  B81C2201/0142

Abstract: A semiconductor chip with embedded microfluidic channels includes a semiconductor substrate, a circuit structure layer, a first microfluidic channel and a micro via hole. The circuit structure layer includes a first metal layer, a first insulation layer and a second metal layer sequentially disposed on a substrate surface of the semiconductor substrate along a stacking direction. A plurality of first bridge patterns penetrates the first insulation layer, and are each electrically connected to the first metal layer and/or the second metal layer. The first microfluidic channel and the micro via hole are embedded in the circuit structure layer. In the stacking direction, a first height of the first microfluidic channel is equal to a first thickness of the first metal layer. In any direction parallel to the substrate surface, a hole width of the micro via hole is equal to a pattern width of each of the first bridge patterns.

公开(公告)号：US08932874B2

公开(公告)日：2015-01-13

申请号：US14322009

申请日：2014-07-02

Applicant: Nalco Company

Inventor： Amy M. Tseng ,  Brian V. Jenkins ,  Robert M. Mack

IPC: G01N21/75 ,  G01N31/22 ,  G01N35/08 ,  B81C1/00 ,  H01L21/67 ,  C09K13/00

CPC classification number: G01N31/221 ,  B81C1/00531 ,  B81C2201/0132 ,  B81C2201/0142 ,  C09K13/00 ,  G01N21/272 ,  G01N21/80 ,  G01N35/085 ,  G01N2021/8411 ,  G01N2021/8557 ,  H01L21/67063 ,  H01L22/12 ,  Y10T436/153333

Abstract: The invention is directed towards methods and compositions for identifying the amount of ammonium acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of ammonium acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of ammonium acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the ammonium acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract translation: 本发明涉及用于鉴定缓冲氧化物蚀刻组合物中的铵酸的量的方法和组合物。 在缓冲氧化物蚀刻组合物中，非常难以测量铵酸的量，因为其具有不同的平衡，并且它是有毒的，因此难以处理和取样。 然而，当用于制造微芯片时，不正确量的铵酸将破坏这些芯片。 本发明利用与添加的显色剂接触时光谱测量铵酸的独特方法，以获得准确，立即和安全的精确测量。

公开(公告)号：US08709268B2

公开(公告)日：2014-04-29

申请号：US13674482

申请日：2012-11-12

Applicant: SPTS Technologies Limited

Inventor： Oliver James Ansell

IPC: G01L21/30 ,  G01R31/00

CPC classification number: H01J37/32963 ,  B81C99/0065 ,  B81C2201/0135 ,  B81C2201/0142 ,  H01J37/32972 ,  H01L22/26

Abstract: A method of etching the whole width of a substrate to expose buried features is disclosed. The method includes etching a face of a substrate across its width to achieve substantially uniform removal of material; illuminating the etched face during the etch process; applying edge detection techniques to light reflected or scattered from the face to detect the appearances of buried features; and modifying the etch in response to the detection of the buried feature. An etching apparatus for etching substrate across its width to expose buried is also disclosed.

Abstract translation: 公开了一种蚀刻衬底的整个宽度以暴露掩埋特征的方法。 该方法包括在其宽度上蚀刻衬底的表面以实现材料的基本上均匀的去除; 在蚀刻过程中照射蚀刻的面; 将边缘检测技术应用于从脸部反射或散射的光，以检测埋藏特征的外观; 以及响应于所述掩埋特征的检测来修改所述蚀刻。 还公开了一种用于蚀刻衬底跨越其宽度以暴露掩埋的蚀刻装置。

公开(公告)号：US20140069185A1

公开(公告)日：2014-03-13

申请号：US13607352

申请日：2012-09-07

Applicant: Xiang Zheng Tu

Inventor： Xiang Zheng Tu

IPC: G01F1/688 ,  H01L35/34 ,  G01F1/692

CPC classification number: G01F1/692 ,  B81C1/00158 ,  B81C1/00246 ,  B81C1/00571 ,  B81C2201/0115 ,  B81C2201/0142 ,  G01F1/6845 ,  G01F1/688 ,  H01L21/3063 ,  H01L35/34

Abstract: A vacuum-cavity-insulated flow sensor and related fabrication method are described. The sensor comprises a porous silicon wall with numerous vacuum-pores which is created in a silicon substrate, a porous silicon membrane with numerous vacuum-pores which is surrounded and supported by the porous silicon wall, and a cavity with a vacuum-space which is disposed beneath the porous silicon membrane and surrounded by the porous silicon wall. The fabrication method includes porous silicon formation and silicon polishing in HF solution.

Abstract translation: 描述了真空腔绝缘流量传感器及相关的制造方法。 传感器包括具有许多真空孔的多孔硅壁，其形成于硅衬底中，多孔硅膜具有许多真空孔，该多孔硅膜被多孔硅壁包围和支撑，以及具有真空空间的空腔， 设置在多孔硅膜下方并被多孔硅壁包围。 制造方法包括HF溶液中的多孔硅形成和硅研磨。

公开(公告)号：US08564026B2

公开(公告)日：2013-10-22

申请号：US13248087

申请日：2011-09-29

Applicant: Franz-Peter Kalz

Inventor： Franz-Peter Kalz

IPC: G01N29/02

CPC classification number: B81C1/00801 ,  B23K2103/50 ,  B81C2201/0142 ,  B81C2201/0143

Abstract: In various embodiments, a chip may include a substrate; a coating, the coating covering the substrate at least partially and the coating being designed for being stripped at least partially by means of laser ablation; wherein between the substrate and the coating, a laser detector layer is arranged at least partially, the laser detector layer being designed for generating a detector signal for ending the laser ablation.

Abstract translation: 在各种实施例中，芯片可以包括衬底; 涂层，所述涂层至少部分地覆盖所述基底，并且所述涂层被设计为至少部分地通过激光烧蚀剥离; 其中在所述基底和所述涂层之间，至少部分地布置有激光检测器层，所述激光检测器层被设计为产生用于结束所述激光烧蚀的检测器信号。